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Topic about latch unlatch

New open topic, not to disturbance the sequence of the original. Good topic mainly, for to be analitic and conscience of the importance of as to programming.

It placed the justifications and it explained.
But I lost, not meeting the meaning real inside of the text.
It could insert the conclusion, briefly.

It affirms that latch/unlatch exactly possesss "memory retentive" with power-down?

I am sure Ron will explain this better but I will try.

The PLC can/will retain latch, unlatch or any retentive memory IF the power to the input devices doesnt change the conditions before the power to the plc is removed.

PLC's may use DC power supplies or a UPS which will allow them to stay on for several scan cycles after "main" power has been lost. This in turn could allow input devices, especially if using a different power source, to show false when they should be true and vice versa.

The idea is to understand the "WHAT IF's" involved with retentive memory and power loss.

dandrade said:

It affirms that latch/unlatch exactly possesss "memory retentive" with power-down?

Click to expand...

In addition to what rsrodan said, Usually (depending on the PLC) the Latched relay will only remain latched through a power cycle only if the PLC memory for that bit is set to be retenitave. Otherwise the latched relay will become unlatched when the PLC power is removed.

Greetings dandrade,

the other guys have already given you the correct answer ... but since you asked me personally, I’ll also add in my way of explaining it ...

first of all ... this is only intended for an Allen-Bradley PLC-5 or SLC-500 system ... other systems may be different ...

you said:

It affirms that latch/unlatch exactly possesss "memory retentive" with power-down?

Click to expand...

if I understand your English correctly, the answer is “YES, that is exactly the big idea that we’re discussing here.”

in very basic terms, with a “seal-in” type of construction, the PLC processor will “forget” the ON status of a bit after the power to the processor is cycled OFF and then back ON ... we could say that the PLC does NOT “retain” the memory ...

but ...

again in very basic terms, with a “latch-on” type of construction, the PLC processor will still “remember” the ON status of a bit after the power to the processor is cycled OFF and then back ON ... we could say that the PLC DOES “retain” the memory ...

the main ! SAFETY ! ISSUE ! that I keep harping about is that SOMETIMES we DO want an output to come back on again after a power cycle ...

but ... SOMETIMES we do NOT want an output to come back on again after a power cycle ...

so we could say that sometimes the “retain memory” is a GOOD thing ... but at other times the “retain memory” is a BAD thing ...

so the programmer has to decide which way he wants the processor to respond ... “retain” or “NOT retain” ... and then the programmer has to know how to properly construct the rungs to obtain the correct response ...

the scary part is that many programmers never bother to consider what will happen to the machine in the event of a power cycle ... they are usually content just to get the machine working correctly with the power ON ... this can be very dangerous in some situations ...

I hope that I have adequately answered your question ... please post again if I have failed ... I will be glad to try again ...

I confirmed. In a long text, the times become not easy, to separate the explanation of the conclusion.Tranks all.

Additional point of comment, I always considered that with POWER-OFF =>POWER-ON, reset all the Bits, words that not RETENTIVE are classfication as memory (sic RAM). Then, it can say that for THESE PLCS it attributes LATCH = MEMORY RETENTIVE.

Always, I considered the comment of this state in situation RUN-STOP, where frequent it does not pass for RESET (CLEAR).
Now, this will be an additional point of evaluation criterion.

********************* More advanced *****************************
It is a fact, little common. Good it would be to enter in contact with the Eng. eletronics of Allen-Bradley (PLC-5 or SLC-500.)
To get a confirmation, of the cycle of processing in this situation.

Already it verified, bits special, capable to signal this event?

In my opinion , the compiler remakes the addressing attribution, transferring to all COIL LATCH to retentive region, being able to occupy TWO addresses, being occult to the programmer.

Being a PLC is BIG, the architecture can be differentiated.