another Emulate question

katratzi

Member
Join Date
Mar 2005
Posts
210
I'm not one to keep asking for help, but this one has really got
me. I have a very simple RSLogix 5 program running on my laptop
using RSLogix Emulate. I cannot get a CTU to increase its accumulated value, even though I can see the rung transitioning
from true to false. (i'm using a TON/EN bit to do this.) I am
trying to use the CTU/DN bit to move a numeric value into an
integer file, but the MOV instruction is not executing even if I
toggle the CTU/DN bit. Is there something that needs to be done
to cause these instructions to be enabled? The timer seems to be working just fine.
 
rdrast is absolutely correct ... if your "problem" code is located in any ladder file other than #2, then you must provide some method to tell the processor to scan the rungs in that "other" file ... usually we install a JSR on an unconditional rung in ladder file #2 ... tip: when the JSR asks for "input" and "return" parameters, just press the Enter key to ignore that part and move on ...

i'm using a TON/EN bit to do this

this sounds a little fishy ... did you mean to say TON/DN bit instead? ...

if nothing seems to help, you might want to post your .RSP program file ... we'll be glad to take a look at it ...
 
yes- all of the code is in ladder 2 (only 7 rungs). I have used
both the DN and EN bits of the timer, but neither will seem to work to increase the accumulated value in the counter. The thing is, I have slowedthe timer down, or latched another bit long enough to actually see it transition, but the counter stays at zero. As soon
as I figure out how I'll post the program.
 
Thanks Ron and rdrast. my program is working now, though I am not exactly sure why. It was very similar to the program rdrast sent
to me, although I didn't use a bit to initiate the timer. The only change I made in my program was to move the C5:0 RES instruction to the last rung, instead of the rung immediately after the counter.
And what the hey, it started working!? I tried attaching my
program to this reply but my evaluation version of Winzip is giving
me an error message, "failed to compress file footagecount0.rsp" so
now I've got to look into that. thanks a bunch for all the help.
 
glad you got it working ... and be sure to get your WinZip working before the next time ... but just for the record, here’s another way to “show us the ladder” ... just use Shift-Click to highlight all of the rungs in question ... then Copy them to the Windows Clipboard ... then Paste them into your reply ... it ain’t glamorous but it gets the job done ... those of us with RSLogix can then Copy-and-Paste the text into a blank program and good magic happens ... for example: the text below is the program that rdrast posted ... SOR is “start of rung” ... EOR is “end of rung” ... etc. ...



SOR XIC B3/0 XIO T4:0/DN TON T4:0 0.01 100 0 EOR SOR XIC T4:0/DN CTU C5:0 10 0 EOR SOR XIC C5:0/DN ONS B3/16 MOV N7:0 N7:10 EOR SOR XIC B3/1 BST RES C5:0 NXB OTU B3/1 NXB ADD 1 N7:0 N7:0 BND EOR SOR END EOR
 
katratzi said:
Thanks Ron and rdrast. my program is working now, though I am not exactly sure why. It was very similar to the program rdrast sent
to me, although I didn't use a bit to initiate the timer. The only change I made in my program was to move the C5:0 RES instruction to the last rung, instead of the rung immediately after the counter.
And what the hey, it started working!? I tried attaching my
program to this reply but my evaluation version of Winzip is giving
me an error message, "failed to compress file footagecount0.rsp" so
now I've got to look into that. thanks a bunch for all the help.

Without seeing your program, it sounds like you had the counter reset triggerred off of the counter done bit, BEFORE you tried your move. That definately won't work (in AB PLC's).

Just for a bit of information, PLC's from different manufacturers (and PLC's from the same manufacturer) often opererate quite differently from one another. It is important to read about how they process their scans to avoid problems like this in the future.

With most PLC's out there today, any change to a bit or word done in a program becomes affective immediately. In your case, that is reflected by the RES instruction clearing not only the counter, but resetting it's .DN bit immediately. Any following logic will never see the .DN bit set. There are ways around that, if you wish, one would be to move your SOR XIC C5:0.DN RES C5:0 EOR run to the rung just BEFORE the actual counter rung. If you do that, then the entire program will see the counter .DN bit active for one complete scan, before the reset.

I say most PLC's, because not all operate this way. Some don't actually process the actual 'RESET' command until it's corresponding counter logic block is executed again. Some self-reset, set a 'DONE' status, and wait for you to manually clear it.

Even I/O isn't always scanned the same way. In typical Synchronous-I/O PLC's, Inputs are scanned before the start of the logic, and copied into a 'Shadow Input Table', then the logic runs, using the state of the inputs before the logic scan, and updating outputs in a 'Shadow Output Table'. At the end of the scan, the 'Shadow Output Table' is copied to the actual physical outputs. Some PLC's though (ControlLogix for one) have an Asynchronous I/O scan. With CLX, the state of an input can change at any time during the logic scan.

Moral of the story, pay some attention to the manufacturers published literature before programming!

Good luck!
 
Here's the "shift-click" version of that program. Rung #5 WAS

immediately after rung #1 so that must have been the problem,
that the counter was being reset before the rest of the program
"saw" it. Not only that but I had placed an unecessary T4:1 RES
in the second rung after the timer which I had to remove (the rung). The thing was, even though this RES instruction was clearingthis DN bit before the rest of the rungs could use it, you couldwatch the program run in Emulate and you could actually SEE theT4:1/DN bit turn green on the rung in front of thecounter, but thecounter wouldn't budge. That, coupled with the fact that I had madethe (wrong) assumption that the DN bit stayed true for one scan, was makin' me nuts.
- charles

SOR XIO T4:1/DN TON T4:1 0.01 1 0 EOR
SOR XIC T4:1/DN CTU C5:0 5 1 EOR
SOR XIC C5:0/DN MOV 30 N10:1 EOR
SOR XIC C5:0/DN ADD N11:1 N10:1 N12:1 EOR
SOR COP #N12:1 #N11:1 10 EOR
SOR XIC C5:0/DN OTE B3/5 EOR
SOR XIC B3/5 RES C5:0 EOR
SOR END EOR
 

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