Bit shift register for Siemens S7

Dutchass

Member
Join Date
Mar 2005
Location
The netherlands
Posts
11
I'm wondering if there is a standard FC for a bit shift register.

What i want:
bit shift register of 64 bits
Clock input to shift all bits 1 place to the left
Before shifting i want to be able to influence each bit seperatly.
(I want to be able to alter bit 12 and 60 before a want the register to shift)


Anyone who can help me out?
 
Hi Dutchass

Try FC92 from the Standard Library / TI - S7 Converting Functions. This is a bit shift register. You can specify exactly where you want the register to be located (in a data block, in M-memory etc) and how long you want it to be. Since you choose the location, you can also influence every bit in the register if you wish.

For example, if you say the register is 64 bits long starting at address M20.0, then the 12th bit in that register will be M21.3 (I think).

Regards

Ken
 
Here's the STL source code for a 64 bit shift register using data at the start of DB1000:

FUNCTION FC 6 : VOID
TITLE =shift bits in DB1000 starting at bit 0
VERSION : 0.1


VAR_OUTPUT
END_VAR
VAR_TEMP
iLoopCount : INT ;
ar1dec : DWORD ;
END_VAR
BEGIN
NETWORK
TITLE =64 bit shift register

// do stuff with bits 12 and 60 to start...

//shift operates as follows:
//shift bit 62 to 63
//shift bit 61 to 62
//..etc
//shift bit 0 to 1
//fill bit 0 with 0
L P#0.1; //bit pointer
NEGD ; //bit pointer decrement
T #ar1dec;
OPN "dbShift";
L 62; //loop 62 times
LAR1 ;
lopa: T #iLoopCount;
A DBX [AR1,P#0.0];
= DBX [AR1,P#0.1];
L #ar1dec;
+AR1 ;
L #iLoopCount;
LOOP lopa;
A DBX [AR1,P#0.0]; //final shift
= DBX [AR1,P#0.1];
SET ;
R DBX [AR1,P#0.0]; //clear first bit
END_FUNCTION
 
I agree the dword shift is quicker but if you want to the bits to be in order in a data block, loading dwords and shifting them in the accumulator will not give the desired result in the data block.
 
I'm obviously not a real engineer!

Someone says "Give me a tool for this job" so I think I'm doing the right thing by passing him the ready-made tool for the job. However, the real engineers among us start to build a tool from scratch, and then begin a debate about what the best kind of tool would be, and the advantages and disadvantages of different kinds of tools.

I actually drifted sideways in to PLC work many years ago with little previous engineering experience. Every so often I come across issues like this that remind me I'm not really one of you - there's a different mind-set at work here! But it's fascinating to watch and learn.

Regards

Ken.
 
Ken M said:
I'm obviously not a real engineer!

Someone says "Give me a tool for this job" so I think I'm doing the right thing by passing him the ready-made tool for the job. However, the real engineers among us start to build a tool from scratch, and then begin a debate about what the best kind of tool would be, and the advantages and disadvantages of different kinds of tools.

:ROFLMAO: :ROFLMAO: :ROFLMAO:
 
You Are Right

SimonGoldsworthy said:
I agree the dword shift is quicker but if you want to the bits to be in order in a data block, loading dwords and shifting them in the accumulator will not give the desired result in the data block.

But you can still shift the data by bytes. This is a good example of why I hate big endian. This would be a simple chore with a little endian processor.
 
Originally posted by Peter Nachtwey:

This is a good example of why I hate big endian.

OK, now I have to ask. What is the benefit of the big endian data format? I'm assuming there is one as I can't believe processor designers would have come up with the layout if there wasn't. Most people I know, including me, find little endian more intuitive.

Just curious.
Keith
 
Last edited:
Just for reference (or confusion as the case may be), here are the bit patterns required in the accumulator to correspond to bits in a data block for a 32bit dword (starting at DBD0).

L DW#16#1
T DB1000.DBD 0 //dbx3.0
L DW#16#10
T DB1000.DBD 0 //dbx3.4
L DW#16#80
T DB1000.DBD 0 //dbx3.7
L DW#16#100
T DB1000.DBD 0 //dbx2.0
L DW#16#1000
T DB1000.DBD 0 //dbx2.4
L DW#16#8000
T DB1000.DBD 0 //dbx2.7
L DW#16#10000
T DB1000.DBD 0 //dbx1.0
L DW#16#100000
T DB1000.DBD 0 //dbx1.4
L DW#16#800000
T DB1000.DBD 0 //dbx1.7
L DW#16#1000000
T DB1000.DBD 0 //dbx0.0
L DW#16#10000000
T DB1000.DBD 0 //dbx0.4
L DW#16#80000000
T DB1000.DBD 0 //dbx0.7
 
Shifting the accumulator is the quickest way of implementing a 64bit shift register (as suggested by Peter Nachtwey), see code below. The key is the "CAD" instruction which changes the order of the bytes in the accumulator.
Using the plc simulator on my laptop gave the following scan times calling the shift register function 5000 times:

820ms - Using siemens FC92
266ms - Using previously posted code which shifts bits one by one
23ms - Using code below !

FUNCTION FC 6 : VOID
TITLE =shift bits in DB1000 starting at bit 0
VERSION : 0.1


VAR_TEMP
iLoopCount : INT ;
ar1dec : DWORD ;
iLoop2Count : INT ;
iLoop3Count : INT ;
END_VAR
BEGIN
NETWORK
TITLE =64 bit shift

OPN "dbShift"; //open data db
L DBD 0; //get lower 32 bits
CAD ; //acc now same order as in data block
SLD 1; //shift left 1 bit
CAD ; //back into order for storing in data block
T DBD 0; //store lower 32 bits
L DBD 4; //get upper 32 bits
CAD ; //acc now same order as in data block
JP sone; //if 1 shifted from lower 32 bits then jump else
SLD 1; //not, so shift left 1 bit
JU past; //and continue
sone: SLD 1; //1 shifted from lower 32 bits so shift left 1 bit
OD DW#16#1; //and now make lsb 1
past: CAD ; //back into order for storing in data block
T DBD 4; //store upper 32 bits
END_FUNCTION
 
Excellent! Nice discovery!

Now look into the RLDA instruction.
LADDER]
L DBD 0; //get lower 32 bits
CAD ; //acc now same order as in data block
SLD 1; //shift left 1 bit
CAD ; //back into order for storing in data block
T DBD 0; //store lower 32 bits
L DBD 4; //get upper 32 bits
CAD ; //acc now same order as in data block
RLDA 1; //rotate cc1 into the lsb
CAD ; //back into order for storing in data block
T DBD 4; //store upper 32 bits[/LADDER]
Phil, code and /code don't work like they used to.

What is the benefit of the big endian data format?

Keith, I have no idea. Some engineers are brain dead and don't see the consequences of their design decisions. Actually, I think it goes back to the dark ages when programmers looked at hex dumps by bytes and they wanted the bytes in order. This is a pretty lame excuse, but my first debugger had a D AAAA,LLLL command that would do a hex dump ( display ) of bytes at hex address AAAA for a length of LLLL. Later commands like DB, DW, and DD commands were added that display words, and dwords in the right order so then it made no difference if the CPU was big or little endian.

I am beginning to do some PowerPC programming now. It has load and store instructions that do the equivalent of a L and CAD or CAD and T instruction in the S7-300. In any case, extra instructions are required to make up for the 'deficiency' of the big endian processor.
 
Last edited:

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