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Reed

Member
Join Date
Aug 2005
Location
South Carolina
Posts
2
I am developing a program for a machine using RS Logics that has a table that travels left and right and is trigered by a prox.I have been using the following code. If OTE is on the table is going left and if OTE is off the table is going right
SOR XIC B3/0 ONS B3/1 OTE B3/2 EOR SOR XIC B3/2 XIC B3/3 OTE B3/4 EOR SOR BST XIC B3/2 NXB XIC B3/3 BND XIO B3/4 OTE B3/3 EOR
but would prefer to use two outputs so I could have a left right and off mode.


Thanks
 
It depends on what is actually moving the table.

If it is a cylinder w/ 2 position valve, then you will need to change the valve to a 3 position w/ blocked center to stop the motion when there is no signal.

If it is an electronic drive, you still have to check the interface to see if it will stop commanding the motor when the signal is taken away.

Which of the outputs in your code is for table left? Can't tell from your post.
 
What you need is a device called a flip-flop. Do a search on this site on flip flops. Hundreds of students have asked for help through this, we glady help, but we don't do their homework. Your code looks like you gave it a good try, and we like to see that. When there is effort there are many who are willing to help. Check out the posts on flip flops and look at the following:

flipflop823.GIF

(code for SLC500 - you appear to be using a MicroLogix so change the OSR to an ONS and adjust the file numbers as needed.)

Alternatively, while I wouldn't recommend this approach for an assignement (because its not what the instructor is looking for), it is a really neat trick to use and if you can understand it you're off to a good start. But it is a slick way to implement a flip flop using a counter.

SOR XIC B3/0 CTU C5:0 0 0 EOR

The flip-flop bit is C5:0.ACC/0, the zero bit of the Accumulator. It will change state 0/1 each time the counter increments. Resetting the counter will turn the bit off, but it is not generally necessary.

It would drive an output like this:
SOR XIC C5:0.ACC/0 OTE O:0/0 EOR
 
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