PLC5 TON question

Can anyone tell me (from the attached file) if the timer "DN" bit
is still set two three or four rungs below the TON rung itself?

In other words once the timer times out and the "DN" bit is set does this reset the timer through the XIO bit before some or all of
the XIC bit instructions that follow are executed?

The DN bit will stay true for one full scan( the way you have it programmed. So the rungs below will work for you.

Timer done will be high for Full single scan when the timer reaches its preset, on the next scan the done bits will be reseted

Praveen

So are we saying that all of the "DN" bits on higher numbered rungs than the timer itself get their state changed but the one in series with the timer does not until the next scan?

I thought I/O changed at the end of the scan but internal logic changed immediately.

The scan works through the program linear, by the time it has set the DN bit, it has already passed the N/C DN bit in series, therefore it will not effect it.

It's like closing the stable door after the horse has bolted.

That just dawned on me! A litle (lot) slow tonight.

Thanks everyone

Its first thing here, so fresh as a daisy..

Greetings to all ...

this is probably overkill, but it looks like there might have been some amount of confusion about the Done bit's status on "rungs-before-the-TON" compared with "rungs-after-the-TON" ... the figure below should clear up any remaining confusion ...

the basic idea is that the processor will only act upon (change) the status of the timer's Done bit when (and only when) the TON instruction is actually executed ... if you keep that in mind, then it's pretty straightforward to see that all of the counters in the program above will always have identical values stored in their accumulators ... specifically, once the processor has changed the status of the timer's Done bit to either a "1" or to a "0", then that particular status will remain "as is" until the next occasion that the TON instruction is executed ... so whether the counter is located above or below the TON instruction in the rung order makes no difference ...



and to scottsull:

I thought I/O changed at the end of the scan but internal logic changed immediately.

Click to expand...

taken at “face value” that statement can lead to a LOT of false conclusions ... one major source of confusion is defining exactly what we mean by the term “I/O” and the term “internal logic” and the term “changed” and the term “scan” ...



if you’re interested in following up on this discussion, it would be a good idea to read this post for a basic overview of the ideas involved ...

hope this helps ...

Ron - it's possible, and indeed even likely, that the counters' RES instructions will happen under conditions which are different from each other (else why have multiple counters). Even though the accumulated counts are shown as identical in this segment of code I bet they end up being different in actual use.

Greetings Bernie,



you’re correct of course ... but the example that I gave was intended to show how the processor manipulates the timer’s Done bit ONLY when the TON is actually executed - and NOT at the end of the “scan” sequence as many beginners wrongly assume ... in other words, the screen shot that I posted was meant to be simple example for discussion purposes - and not a valid programming technique ...



sorry if I didn’t make that perfectly clear ... and thanks for keeping me straight ...



note: actually I first started out by using ADD statements to increment a series of “test” values ... I decided that the Counters would make more sense to most beginners - at the risk of having the “Reset” issues which might (and obviously did) come up ...

Ron, that little program was funny. I did the same thing years ago to see exactly what would happen if you tried that on a Mitisubitshi PLC. Funny thing was,the Mitisubitshi would only count AFTER the timer rung not before it. Have no clue why but after I did that little test I just kept it in my mind that would happen.

I did the same thing years ago to see exactly what would happen if you tried that on a Mitisubitshi PLC.

Click to expand...

I've always been a firm believer in the power of experimentation, Clay ... one size does NOT fit all ... your mileage may vary ... and not all PLCs scan the same ...

Ron Beaufort said:

and not all PLCs scan the same ...

Click to expand...

About six years ago, a frequent client built a control system that was similar to an old one I had designed just prior to that time.

Instead of paying me (I was the sub-contracting controls engineer who did the original project) this company's electrical tech took my old program and changed the I/O accordingly to fit the new application. My memory escapes me, but I think they went from SLC500 fixed to modular (5/02, 5/03, or 5/04) or perhaps to a MicroLogix. Anyway they couldn't get anything to work.

The reason: There were many, many timers in the program which were "retentive" i.e. required RES instructions which were located ahead of and after the timer rungs. They called me in, and I rearranged the resets to work properly, based on how this particular processor scanned.

MORAL: See Ron's quote above!

PS My original program wasn't "sloppy". The logic for the reset made sense to be where they were for clarity. Obviously, this went out the window later out of necessity.