How fast is PLC5 Input module?

flyers

Member
Join Date
Sep 2006
Location
Amk
Posts
295
Hi guys,

I've an new aplication to be added into the existing system where the sensor will send 2000 pulse/signal to the PLC-5/60 in every minute, equal to 33 pulse/singal per second.

Can a normal input module able to read at this input frequency? I can't find any details on the 1771-IBN input frequency.

Any comments?
 
This depends upon the scantime & module update time if the module is in the RIO comunication then the communication delay will add up

The specific of IBN

IBN.JPG
 
rPraveenkum said:
Better try with high speed counter modules

Hi,

Based on the Input signal delay (worst case):

In layman terms:

1) low to high is 8ms, this means the IBN Module is only able to detect the pulse/signal from the sensor from 0 to 1, if the signal maintain for 8ms. If the pulse/signal just come in for 2 or 3 ms the IBN will not be able to detect it, am i right?

2) high to low is 8ms, this means the IBN will only update the CPU after 8ms when the pulse/signal is OFF (or 0)?

Assume the scan time is 3 - 4 ms and the IBN is in the local rack.

Do I understand correctly? Thank you.
 
flyers said:
1) low to high is 8ms, this means the IBN Module is only able to detect the pulse/signal from the sensor from 0 to 1, if the signal maintain for 8ms. If the pulse/signal just come in for 2 or 3 ms the IBN will not be able to detect it, am i right?
yes


flyers said:
2) high to low is 8ms, this means the IBN will only update the CPU after 8ms when the pulse/signal is OFF (or 0)?
yes

flyers said:
Assume the scan time is 3 - 4 ms and the IBN is in the local rack.

not only that IO scan & also the Program scan


high speed counter modules do counting in the module itself

But for IBN counting done in the processor. so it include the total program scan
 
Check out whether 5/60 support PII or not. If yes, counting 33 pulses per second is not an issue at all.

___________
 
If the program scan is 3-4ms AND the input is a local DC type AND the on time and off time are 15 milliseconds (or greater than 8ms possible delay at the input + 4ms worst scan time), it would work.

Instead of a PII, you can use an STI* routine to guarantee a fixed, short scan time for the logic that counts pulses. Use this method carefully, and make your logic within the STI file as efficient as possible. It can cause the scan rate of the main program to become quite variable depending on how many interruptions occur per main scan, and how much difference there is in the minimum and maximum scan time of the STI logic.

*(selectable timed interrupt)
I have done this up to a frequency of 25Hz with an STI setting of 5ms with no problems, other than a main scan time which varied randomly from 22ms to 35ms instead of a steady 20ms. In my case that did not cause other issues.
 
I forgot to mention that the IIN instruction will be required to update the input card each time the STI is executed otherwise the inputs will inly be refreshed at the end of each main program scan...
 
chavak said:
Check out whether 5/60 support PII or not. If yes, counting 33 pulses per second is not an issue at all.

___________

Hi,

Sorry, I've not use any PII before, is that an instruction? I tried to find it in the reference manual but can't locate it.
 
OkiePC said:
If the program scan is 3-4ms AND the input is a local DC type AND the on time and off time are 15 milliseconds (or greater than 8ms possible delay at the input + 4ms worst scan time), it would work.

Instead of a PII, you can use an STI* routine to guarantee a fixed, short scan time for the logic that counts pulses. Use this method carefully, and make your logic within the STI file as efficient as possible. It can cause the scan rate of the main program to become quite variable depending on how many interruptions occur per main scan, and how much difference there is in the minimum and maximum scan time of the STI logic.

*(selectable timed interrupt)
I have done this up to a frequency of 25Hz with an STI setting of 5ms with no problems, other than a main scan time which varied randomly from 22ms to 35ms instead of a steady 20ms. In my case that did not cause other issues.

Thank you for highlighting.
 
Under the processor status tab-> click PII then press 'F1' for help file

It shows

PLC5 PII Status Overview
______________________
Tip
Interrogate the status file when the processor faults to determine the cause of the error. A quick method to call the status file when the processor has faulted is to click the drop-down arrow to the right of the Operational mode list box in the online bar. Then click Goto Error
The PII tab allows you to monitor configured settings for a processor input interrupt.
Fields on this display that are in gray are read-only. Fields shown in white are read/write. However, this information is seldom written to by the user program or programming device (unless you want to reset or clear a function). If you write to status file data, make sure that you first understand the function fully.
This information appears on the PII tab with the Structured Radix selected.
Access this dialog by double-clicking the Processor Status icon in the project tree or double-clicking the status (S2) file. Then select the PII tab to give it focus.
Click here for a list of the fields on the dialog and their definitions.

PII Status Parameter
__________________
What's on the dialog?
Preset S:50
This field contains a value that determines how many conditions you want to occur before the interrupt. The valid range is 0-32767. A zero or a one in this field means the interrupt will occur every time.
Events since Last Interrupt S:52
This field contains the number of PII events (the input conditions that caused the interrupt) since the last interrupt.
File Number S:46
This field contains the number of the program file that contains the PII program.
Module Group S:47
This field contains the assigned rack number and I/O group number of the input to monitor (for example 21 represents rack 2, group 1). This is valid only for inputs in the processor-resident chassis. If the input word number specified is not in the local rack or if there is not an input module in the slot addressed, a minor fault bit (S:10/11) is set at mode transition.
Bit Mask S:48
This field contains a decimal number representing the bit mask for each module group bit (specified in S:47 above). In structured mode this will be a number between 0-32767. To better see or change the masked bits, view this tab in binary mode. Enter a 1 to monitor the bit. Enter a 0 to ignore the bit.
Compare Value S:49
This field contains a decimal number representing the compare value for each module group (specified in S:47 above). Bits in this word are used to control a PII through bit transition. To better see or change the transition bits, view this tab in binary mode. Enter a 1 for a trigger to occur on the false-to-true transition. Enter a 0 for a trigger to occur on the true-to-false transition. (In structured mode this will be a number between 0-32767.)
PII Changed Bits S:51
This field displays the bit transitions that caused the interrupt. You can use this information to condition other rungs in your ladder program.
If one of these bits is already set (i.e., a previous interrupt set the bit), the processor sets a minor fault (S:10/12) to indicate a possible PII overlap. If you want to monitor this overlap, make sure the last rung in your PII program clears this return mask in the status file.
Last Scan Time [x1 ms] S:55
This field contains the time it took for the current or last scan of the PII.
Max Observed Scan Time [x1 ms] S:56
This field contains the longest time that was ever displayed in the Last Scan field for a specific PII.
Warning:
Word not in Local Rack S:10/11
This field is checked if the input word number specified is not in the local rack or if there is not an input module in the slot addressed (S:47).
No Command Blocks S:10/13
This box is checked if no command blocks exist to get the Processor Input Interrupt. You can use the processor's internal counter or bit transition to execute the PII.
User Routine Overlap S:10/12
This box is checked if a set condition exists in the PII return mask or accumulator bits (possibly set by a previous interrupt) before completing the currently executing PII interrupt routine. PII return mask changed bits (S:51) are retentive. It may be necessary to place a MOV instruction on the last rung in the PII file. Move 0 in S:51 to reset the PII bits before finishing the PII file. If this is not done, a PII overlap bit will be set on that status page, causing this minor fault.
Rockwell Software Inc., 1997, 1998, 1999, 2000

_____

Basically you need to create a new ladder file say Ladder_30, define the ladder file in the Processor status window + define the inputs to be interrupted with the right bit mask.

So for a changed input status, the status bits will be changed in the processor. Say your input is tied to Input 0, then the addressing in ladder 30 for that input will be S:51/0. Use this to trigger/count what ever you want in the ladder.

If you are using this bit to count, add a non conditional rung above the counter to unlatch the counter/count up bit (eg: OTU C5:0/CU).


Hope this helps
 
chavak said:
Under the processor status tab-> click PII then press 'F1' for help file

It shows

PLC5 PII Status Overview
______________________
Tip
Interrogate the status file when the processor faults to determine the cause of the error. A quick method to call the status file when the processor has faulted is to click the drop-down arrow to the right of the Operational mode list box in the online bar. Then click Goto Error
The PII tab allows you to monitor configured settings for a processor input interrupt.
Fields on this display that are in gray are read-only. Fields shown in white are read/write. However, this information is seldom written to by the user program or programming device (unless you want to reset or clear a function). If you write to status file data, make sure that you first understand the function fully.
This information appears on the PII tab with the Structured Radix selected.
Access this dialog by double-clicking the Processor Status icon in the project tree or double-clicking the status (S2) file. Then select the PII tab to give it focus.
Click here for a list of the fields on the dialog and their definitions.

PII Status Parameter
__________________
What's on the dialog?
Preset S:50
This field contains a value that determines how many conditions you want to occur before the interrupt. The valid range is 0-32767. A zero or a one in this field means the interrupt will occur every time.
Events since Last Interrupt S:52
This field contains the number of PII events (the input conditions that caused the interrupt) since the last interrupt.
File Number S:46
This field contains the number of the program file that contains the PII program.
Module Group S:47
This field contains the assigned rack number and I/O group number of the input to monitor (for example 21 represents rack 2, group 1). This is valid only for inputs in the processor-resident chassis. If the input word number specified is not in the local rack or if there is not an input module in the slot addressed, a minor fault bit (S:10/11) is set at mode transition.
Bit Mask S:48
This field contains a decimal number representing the bit mask for each module group bit (specified in S:47 above). In structured mode this will be a number between 0-32767. To better see or change the masked bits, view this tab in binary mode. Enter a 1 to monitor the bit. Enter a 0 to ignore the bit.
Compare Value S:49
This field contains a decimal number representing the compare value for each module group (specified in S:47 above). Bits in this word are used to control a PII through bit transition. To better see or change the transition bits, view this tab in binary mode. Enter a 1 for a trigger to occur on the false-to-true transition. Enter a 0 for a trigger to occur on the true-to-false transition. (In structured mode this will be a number between 0-32767.)
PII Changed Bits S:51
This field displays the bit transitions that caused the interrupt. You can use this information to condition other rungs in your ladder program.
If one of these bits is already set (i.e., a previous interrupt set the bit), the processor sets a minor fault (S:10/12) to indicate a possible PII overlap. If you want to monitor this overlap, make sure the last rung in your PII program clears this return mask in the status file.
Last Scan Time [x1 ms] S:55
This field contains the time it took for the current or last scan of the PII.
Max Observed Scan Time [x1 ms] S:56
This field contains the longest time that was ever displayed in the Last Scan field for a specific PII.
Warning:
Word not in Local Rack S:10/11
This field is checked if the input word number specified is not in the local rack or if there is not an input module in the slot addressed (S:47).
No Command Blocks S:10/13
This box is checked if no command blocks exist to get the Processor Input Interrupt. You can use the processor's internal counter or bit transition to execute the PII.
User Routine Overlap S:10/12
This box is checked if a set condition exists in the PII return mask or accumulator bits (possibly set by a previous interrupt) before completing the currently executing PII interrupt routine. PII return mask changed bits (S:51) are retentive. It may be necessary to place a MOV instruction on the last rung in the PII file. Move 0 in S:51 to reset the PII bits before finishing the PII file. If this is not done, a PII overlap bit will be set on that status page, causing this minor fault.
Rockwell Software Inc., 1997, 1998, 1999, 2000

_____

Basically you need to create a new ladder file say Ladder_30, define the ladder file in the Processor status window + define the inputs to be interrupted with the right bit mask.

So for a changed input status, the status bits will be changed in the processor. Say your input is tied to Input 0, then the addressing in ladder 30 for that input will be S:51/0. Use this to trigger/count what ever you want in the ladder.

If you are using this bit to count, add a non conditional rung above the counter to unlatch the counter/count up bit (eg: OTU C5:0/CU).


Hope this helps

Thank you for your explaination, really appreciate it. I'll try it out.
 

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