Special Relays 5/04 Processor

I am trying to find special relay like the one that Direct Logic has ( SP0 ). I am not seeing anything like that available in RSLogix. I have an OSR being over looked in my ladder and I think it is because the cpu is not seeing the false to true transistion of the bit before the OSR. how can I get the cpu to take a second look at this rung? is there a special relay in RSLogix that I can use? any help would be appreciated.

Travis

The processor can not miss the false to true transition of your osr.

The only way this is possible is if you have an input that went true to false faster than the processors scan time which is unlikely.

Check your logic, you have something wrong.

You're looking for a first scan.
AB uses a first pass.

If you are looking to execute some logic on the first scan after the CPU starts then use an XIC S:1/15, no one shot required, as this bit is only true for the first scan.

The S:1/15 is often used to pass setup data to analog modules.

Make sure the address that the OSR used is not being used elsewhere and verify that the logic is being executed if its in a subroutine. For debug, add a branch with a OTL instruction and temporary bit address afer the OSR so it will record that the OSR saw the transition.

jstolaruk said:

Make sure the address that the OSR used is not being used elsewhere and verify that the logic is being executed if its in a subroutine. For debug, add a branch with a OTL instruction and temporary bit address afer the OSR so it will record that the OSR saw the transition.

Click to expand...

jstolaruk rung 2 of ladder 10 is the only location of the OSR and the way the logic is in rungs 2 and 3 it is almost in a since like an OTL just because it is a holding circuit, so to speak. If I can just get the cpu to take a second look at this rung I believe it will take care of the problem. it does not happen all the time, only about once a week. And I always just simply toggle the XIC N42:60/1 to start the CIP stage.

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Maybe I am way off base on this, but in rung 1 N40:3/0 is true so it makes the transition from false to true and the same goes for the XIC bit N40:3/0 in rung 2. is it possible that the XIC bit in rung 2 has already made the false to true transition before the scan has seen it( since the scan starts at rung 1)? Not that I disagree with allscott but I can not explain this other than the scan is missig the false to true transition of N40:3/0.

In the ladder you present N40:3/0 is always true. Except for transition to RUN mode it never makes a transition. As far as the OSR is concerned it has ALWAYS been true. If you really want a transition to be seen then preceed the N40:3/0 with a contact of the S:1/15 that Ken Moore advises. This will give one flse pass for the OSR to register. After that N40:3/0 will be on until the program end.

The problem I see here is that if n40:3/0 is not cleared at at least one scan before executing rung 0, the OSR storage bit N41:3/0 will never reset so that the OSR instruction later knows to look for a transition. But your program as shown will never allow it that to happen. What exactly are you trying to achieve? That n42:60/1 get set and sealed on the first scan of the processor until one of the B3 bits get set? If thats true, you need to replace the XIC n40:3/0 with the first scan bit to get this to work everytime.

EDIT: delete the OSR instruction and rung 0 also

First, this is how an OSR works.

I am ignoring rung 0 for now, so let's pretend that we don't know what writes to N43:0/0.

When N43:3/0 goes true, the storage bit N41:3/0 is examined. If it is off, then the rest of the rung is completed (OTE N42:60/0 in your case). N41:3/0 is then set to true.

If, on a subsequent scan, N43:3/0 is false, the storage bit N41:3/0 is cleared and the rest of the rung is treated as false.

Those bits N41:3/0 and N42:60/0 will remain in those states until that rung is scanned again next time. As long as no other logic in the PLC writes to those addresses.

So a false to true transition of N43:3/0 will always result in N42:60/0 being true for exactly one PLC scan starting from rung 1 to and ending there as well.

Your problem has only 3 possible causes:

1. N43:03/0 is not making a false to true transition slow enough for the PLC to detect it. If your scan time is 10ms, and N42:60 is only off for 9.9ms, at some point, it will get missed.

2. N43:03/0 is making a false to true transition while B3:3/2 is on.

3. N43:03/0 is making a false to true transition while B3:5/4 is on.

Those are the only possible ways that N42:60/1 is not being sealed in.

Now, rung 0 will write a 1 to N43:03/0 the first time the program is downloaded and run.

So, you will get one and only one occurence of the oneshot. Cycling power and switchin back and forth from program mode will not create another transition.

N42:60/0 is a first run bit, not a first scan bit in this case.

Okay, if that is not what you want you need to find out what else writes to that address? DONT FORGET TO SEARCH ON THE WHOLE WORD! Maybe there is a CLR N42:60 (or a MOV 0 N42:60) somewhere that resets that bit.

Is this logic is supposed to detect first scan, and seal in rung 2 every time the processor goes into run mode following a power cycle?

If so, on rung 2 replace XIC N42:60/0 with XIC S:1/15 and delete rungs 0 and 1.

I hope this rambling post doesn't add to the confusion...
Paul

You guys have given me alot to look at... I will need to study this some more. the program is quite extensive and I cannot delete N40:3/0 as it is referenced in at least 40 different rungs throughout the code.I feel I have done well finding the problem now I just need to find the solution. The S:1/15 bit, I need a little more explaining on this. If I understand Ken and Bernie correctly this bit will be on for one scan only, but are there other times that the S:1/15 bit will make a transition other than to run mode?

OkiePC- how can I search the whole word? I am still learning this AB stuff.

S:1/15 will be true only for the very first program scan when the PLC goes into RUN or REMOTE RUN mode.

This will happen when:

1. power is applied,
2. when the keyswitch on the processor is cycled from program mode to run mode.
3. when the keyswitch is in the remote mode position and a person with a PC running RSLogix places the processor in REMOTE RUN mode.

It will never happen during normal machine operation unless cycling the power to the plc is part of your normal operation. (don't laugh, I have seen machines wired like that...)

...as it is referenced in at least 40 different rungs...

Click to expand...

Are any of those 40 rungs destructive references? In other words are there any other instructions that write to that bit?

If the answer is yes, then those other rung(s) are an important part of the picture of what is happening that causes your troublesome rung not to work like you expect.

If the answer is no, then you might be able to do a wholesale search and replace with S:1/15.

Before you make any changes though, you need to fully understand the intentions of the programmer who "rolled his own" first run bit.

I'd be interested in helping you sort it out if you can post the whole program...

Paul

OkiePC, I will be glad to post the program for you. the file will not have any rung comments or descriptors though, but I will still post it for you. I will be able to get a file at work when I get back on monday that has all the comments, I just can't do it now we have made some changes to the network and how we access files as to keep the files up to date without a bunch of revisions to look at, and as of yet that project is not complete. so it has things in limbo at the moment. but by all means please have a look and I appreciate the help.

Okay, I have looked at the code and found a second "destructive" instruction writing to the address. After studying this, I don't see how it could ever work correctly. The only JSR 10 in the program is on a branch following XIC B3:1/15 and OTE N40:3/0.



I can't see any way for N40:3/0 to be false during a scan of the OSR instruction in file 10 rung 1.

I suspect that once a week, something else happens to turn on either bit B3:3/2 or B3:5/4 to drop out the seal on file:rung 10:2 and that the rung never seals in by itself.

Try adding these test rungs...MAKE SURE THOSE ADDRESSES I PICKED DON'T BELONG TO AN HMI INTERFACE OR SOMETHING FIRST!



Those OTL instructions will leave behind evidence of the states of the bits affecting your logic. You should toggle them off manually to "set the trap", and then check them when problems occur to help track it down.

AGENTTINFOIL said:

OkiePC- how can I search the whole word? I am still learning this AB stuff.

Click to expand...

Just leave off the bit delimiter "/" and bit number and search for N40:3.

You will then find every reference to that whole word or any of its 16 bits.

The only ones that my not show up in that type of search involve indexed addressing, but that's a whole other subject, and there are method to search for those too. Your program does not appear to use indexed addressing...

Here`s another idea?



Since it`s called in ladder 2 N40:3/0 has to be on while its in this ladder.

Good idea OKiePC and i must learn to type with both hands!