S7 Logic Issue

Hello, I am trying to solve a mysterious problem that is occurring with a 300 S7 processor. I am fairly new to Seimens, I am a AB guy, and have the task of solving an issue that has arisen. A simple bit of code was built involving inline coils and a NOT gate. All logic up to the NOT gate is fine, however, the logic behind it is not correct. I have read over some help files, and the use of the inline coils are against some exceptions for programming but there is a duplicate program running on another piece of equipment that is solving for the logic correctly. I am attaching a zip of the FB network if I can obtain some help.

Thanks

The last statement of network 1 is an and instruction - this and instruction will operate on the next logic which just happens to be in the next network so what you see in the ladder view can be a bit confusing. Whether the code is supposed to be like this is another matter. To make the ladder view correct, remove the A from the end of network 1 and add a n/o coil as the first contact in network 2 using DB117.dbx50.2

Looking on the comments and symbol assignments, I would guess that DB117.DBX50.2 has nothing to do with the logic in network 2.
Looks more like someone forgot something.
I would remove the last "A DB117.DBX50.2" line in network 1, but I would not add it to network 2.

Coman93, what is it that does not work correct ?

The logic of the inline coil and the coil on the end does not go low when the local temp variable "EMG_STOP" is high.

Your posted picture shows the local variable EMG_STOP low - can you post one of it high showing the problem you describe.

I think his point is that the local variable EMG_STOP is shoing low, whilst the preceding logic (1st branch) should make it high.

I was wondering if two mid rung coils in series somehow effect the final logic, what does it look like in STL (I don't have S7 anymore, unfortunatly restricted to ControlLogix at the moment which I found is full of bugs and the program corrupts).

Personally I don't like the logic in that rung.

Post #2 or #3 describes what to do to "fix" this, either

or

"L D[AR2,P#0.0]" is correct.
The "forgotten" AND instruction in network 1 messes with the presumably intended logic of network 2.