magicsmoke
Member
How can I reset the count on a 1746-HSCE card? What does the first rung do? I thought it was suppose to reset the count but it didn't.
Last edited:
AB 1746-HSCE reset count
- Thread starter magicsmoke
- Start date
rsdoran
Lifetime Supporting Member
Try reading the manual Chapter 4, there are some settings that decide how it can be reset: http://literature.rockwellautomation.com/idc/groups/literature/documents/um/1746-um006_-en-p.pdf
Magic 8 Ball
Member
Heres how to figure out what the first rung is doing... first pass bit means it will run once at power up thats it... and affect whatever is in slot 2
Publication 1747-RM001D-EN-P - November 2003
E-20 Data File Organization and Addressing
Addressing M0-M1 Files
The addressing format for M0 and M1 files is below:
Mf:e.s/b
Where
M = module
f = file type (0 or 1)
e = slot (1 to 30)
s = word (0 to max. supplied by module)
b = bit (0 to 15)
Restrictions on Using M0 and M1 Data File Addresses
M0 and M1 data file addresses can be used in all instructions except
the OSR instruction and the instruction parameters noted below:
Monitoring Bit Addresses
SLC 5/02 and Higher Processors with M0 and M1 Monitoring Disabled
When you monitor a ladder program in the run or test mode, the
following bit instructions, addressed to an M0 or M1 file, are indicated
as false regardless of their actual true/false logical state.
Table E.7 Instruction parameters not available for Use with M0 and M1 data File
Addresses
Instruction Parameter (uses file indicator #)
BSL, BSR File (bit array)
SQO, SQC, SQL File (sequencer file)
LFL, LFU LIFO (stack)
FFL, FFU FIFO (stack)
Publication 1747-RM001D-EN-P - November 2003
E-20 Data File Organization and Addressing
Addressing M0-M1 Files
The addressing format for M0 and M1 files is below:
Mf:e.s/b
Where
M = module
f = file type (0 or 1)
e = slot (1 to 30)
s = word (0 to max. supplied by module)
b = bit (0 to 15)
Restrictions on Using M0 and M1 Data File Addresses
M0 and M1 data file addresses can be used in all instructions except
the OSR instruction and the instruction parameters noted below:
Monitoring Bit Addresses
SLC 5/02 and Higher Processors with M0 and M1 Monitoring Disabled
When you monitor a ladder program in the run or test mode, the
following bit instructions, addressed to an M0 or M1 file, are indicated
as false regardless of their actual true/false logical state.
Table E.7 Instruction parameters not available for Use with M0 and M1 data File
Addresses
Instruction Parameter (uses file indicator #)
BSL, BSR File (bit array)
SQO, SQC, SQL File (sequencer file)
LFL, LFU LIFO (stack)
FFL, FFU FIFO (stack)
bernie_carlton
Lifetime Supporting Member + Moderator
During the configuration of the module the "Reset Mode" bits (M0:e.1/5-7) need to be set to allow this "soft reset" to perform. Follow rsdoran's advice to review these settings. Depending on the bits the reset may also require a Limit Switch and/or a 'Z' signal from the encoder to become true also.
It is best to set this bit (assuming the setup mentioned allows it) and wait for I:e.0/12 to be come true (showing reset is TRUE) then reset the 'M' bit.
(e) is the installed slot of the module, in your case "2"
It is best to set this bit (assuming the setup mentioned allows it) and wait for I:e.0/12 to be come true (showing reset is TRUE) then reset the 'M' bit.
(e) is the installed slot of the module, in your case "2"
magicsmoke
Member
OP
thank's you guys that help out alot
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