RS Flip Flop according to IEC 6113.Who is correct: ABB or Siemens? Quite interesting.

thetripathi

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This is what I got from ABB Control Builder Help file about RS flip flop:


How to Use the Function Block

The RS bistable flip-flop, is a latch where the R1 input dominates. If the Set and R1 signals are both True, the output Q1 is False.

Specified in the IEC 61131 standard


This is what I got from S7 Help file about RS flip flop:

Description
The Reset_Set Flip Flop instruction executes instructions such as Set (S) or Reset (R) only when the RLO is 1. An RLO of 0 does not affect these instructions, the address specified in the instruction is not changed.

Reset_Set Flip Flop is reset when the signal state at input R is 1 and the signal state at input S is 0. If input R is 0 and input S is 1, the flip flop is set. If the RLO at both inputs is 1, the flip flop is set.

The Reset_Set Flip Flop instruction is affected by the Master Control Relay (MCR). For more detailed information about how the MCR functions, refer to MCR on/off.

I guess both the explanations are different from each other.Can anyone tell me the exact definition of RS block according to IEC standards.

Thanks
Preet
 
Siemens has the RS-flipflop and the SR-flipflop.

Siemens help file about the SR-fliflop:

SR (Set-Reset Flip Flop) is set if the signal state is "1" at the S input, and "0" at the R input. Otherwise, if the signal state is "0" at the S input and "1" at the R input, the flip flop is reset. If the RLO is "1" at both inputs, the order is of primary importance. The SR flip flop executes first the set instruction then the reset instruction at the specified <address>, so that this address remains reset for the remainder of program scanning.
The S (Set) and R (Reset) instructions are executed only when the RLO is "1". RLO "0" has no effect on these instructions and the address specified in the instruction remains unchanged.

This is identical to the ABB explanation.

The LAD blocks are just graphic representation of the STL code behind it.:

SR-flipflip:

A #set
S #output
A #reset
R #Output

RS-flipflop:

A #reset
R #output
A #set
S #output

It's a top to bottom scan, so they work very differently.

Be carefull which one you choose...
 
thetripathi - is the text you posted copied and pasted directly from the S7 help file ? If so, which version of Step 7 are you using ?
 
I am using S7 V5.4 SP3.by thw way Jeebs the ABB explanation for SR Flip Flop is :
"
The SR bistable flip-flop, is a latch where the S1 input dominates. If the S1 and Reset signals are both True, the output Q1 is True."

I GUESS BOTH ARE DIFFERENT.
 
L D[AR2 said:
thetripathi - is the text you posted copied and pasted directly from the S7 help file ? If so, which version of Step 7 are you using ?

The text he posted is similar to the explanation for the Reset-Set flipflop I found. Using S7 V5.4.

The ABB explanation is similar to the Set-Reset flipflip from Siemens.

Notice the very subtle difference.

EDIT: Cross posted
 
Last edited:
You are right jeebs.Thats what I am asking.How come the IEC definition is different for both ABB and Siemens.Which one is the correct explanation for RS Flip Flop.

I feel in RS, R dominates and when both R & S are "true", R is going to reset the Q( As given by ABB )

same for SR. Here S dominates and when both S & R are True, S is going to Set the Q.( As given by ABB)

which is Vice Versa in Siemens.Means Siemens is not adhering to the IEC for this ??? or how it is ?
 
thetripathi said:
You are right jeebs.Thats what I am asking.How come the IEC definition is different for both ABB and Siemens.Which one is the correct explanation for RS Flip Flop.

I feel in RS, R dominates and when both R & S are "true", R is going to reset the Q( As given by ABB )

same for SR. Here S dominates and when both S & R are True, S is going to Set the Q.( As given by ABB)

which is Vice Versa in Siemens.Means Siemens is not adhering to the IEC for this ??? or how it is ?

I have no experience with ABB, nor very up to date with the IEC definition, but I can tell you:

Siemens use the name according to the sequence the 'Block' is processed:

SR = first Set then Reset. Knowing in Siemens the last scanned statement will be the 'Dominant' one. Here it'll be Reset.
RS = first Reset then Set. Last scanned statement is 'Dominant'. Here Set.

Why the different naming? Who knows.......
 

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