PLC delayed output?

kevilay

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Join Date
Feb 2009
Location
Ontario
Posts
176
I ran into a weird issue with this thing im building. I have input pulses that flash every 1/4 of a second. I want the output to copy that exactly except to do it 1/2 second later. So an example timeline of 3 high input pulses would be

Lets say I is I:0/0 and O is 0:0/0

1/4s 1/2s 3/4s 1s 1(1/4) 1(1/2)
I=1 I=1 I=1 I=0 I=0 I=0
O=0 O=0 O=1 O=1 O=1 O=0

Is this possible to do? I was trying to think of a way to do this and couldnt come up with anything. Im just starting out on PLCs and im working on a final project for school.
 
I have input pulses that flash every 1/4 of a second. I want the output to copy that exactly except to do it 1/2 second later. So an example timeline of 3 high input pulses would be

Lets say I is I:0/0 and O is 0:0/0

1/4s 1/2s 3/4s 1s 1(1/4) 1(1/2)
I=1 I=1 I=1 I=0 I=0 I=0
O=0 O=0 O=1 O=1 O=1 O=0

Is this possible to do?

Yes, read up on (Bit) shift registers. The clock pulse will have to be fast enough for the resolution you desire. And you will need enough bits to = 1/2 second at the resolution you need.
 
How do I shift the bits tho because its not a constant pulse. It can go 3 pulses in 1 and 1/2 sec then one more pulse 2 seconds later. Im familar with bit shift but not certain how you would shift the bits in the case

Kevin
 
Not trying to be a smart a** but, even for a (relatively) simple task as this, a flowchart or some pseudocode would help to visualize what needs to be done, ie.:

When the input changes, store the new value to use during further processing.
 
How do I shift the bits tho because its not a constant pulse. It can go 3 pulses in 1 and 1/2 sec then one more pulse 2 seconds later. Im familar with bit shift but not certain how you would shift the bits in the case

Kevin

Many PLCs have a free-running counter so you could select one of its bits to trigger a shift register instruction.

For example, lets use just one output you want to know what its state was 1/2 second previously. And your free running clock has a bit that goes on every 1/8 second. Copy the output bit's state to a memory word's bit 0. Bit shift that memory word left every 1/8 second. Bit 4 of the memory word will be the output's state 1/2 second ago. Bit 5 would be the state 5/8 second ago. Bit 3 would be the state 3/8 second ago.

For most PLCs, this will take two rungs.

Hope that helps.
 
But consider milldrone's comments. If the pulses are fairly short or if you want a better approximation of 'exactly' 1/2 second after the pulse turns on you may need a finer clock and correspondingly longer shift register (a 1/16 sec clock pulse would require twice as long a shift register etc). The scan rate of your PLC (or possibly an interrupting periodic task) will set a limit on how fine this can go.
 
The time doesnt need to be exactly 1/8th of a second, but it would need to be consistent and adjustable if possible. How do I do the math for it? Is there a thread on how to do this? Im not sure what to search for.

Kevin
 
As Bernie pointed out, do your math carefully. You need to decide on the range of adjust-ability and the accuracy required so you can choose the source of the trigger to use for bit shifting. My earlier description is as close to giving you the plc code as can be without drawing it out.
 
The time doesnt need to be exactly 1/8th of a second, but it would need to be consistent and adjustable

Kevin

As Bernie pointed out, do your math carefully. You need to decide on the range of adjust-ability and the accuracy required so you can choose the source of the trigger to use for bit shifting.

Kevin some of the pitfalls are.

If you choose a trigger source that is too close to your scan time your plc may not do a shift during one scan and this will increase the time between the input and the output of the shift register. The fastest trigger source I would use would be at least two scans long, three or four would be better.

If you chose a trigger that say for instance is 1/8 second. What happens if your input is 1/10 of a second long? One of two things. One possibility is the output from the shift register will now be 1/8 second long and not 1/10 second as the original pulse was. The other possibility is because the input pulse is shorter than the clock pulse it may not be set at the time of the shift. In other words it will not show up in the bit pattern.

For the adjustment, are you referring to the 1/2 second between the input and the output?
 
Last edited:
We still haven't heard from kevilay about the width (the ON time) of each pulse. Can you specify this?

How exactly must the width of the output match the width of the input? That may set your desired clocking rate of the shift register.

You may have to look into STI (Timed interrupts) 'immediate input' and 'immediate output' functions as well as the shift register. That could make it less dependent on scan time but could lock up your PLC with it doing nothing else.
 
Sorry for not being descriptive enough. The input pulse on time will be pretty fast, it will be approximately a 1/4 second. At the absolute maximum it would be 1/8th of a second so Id like to design for that. As for talking about using a clock pulse to shift it, is that using these bits?

S:4/0 to S:4/15 are:
20, 40, 80, 160, 320, 640, 1280, 2560, 5120,
10240, 20480, 40960, 81920, 163840, 327680,
and 655360 ms.

Sorry Im kinda new at this I didnt really cover any sort of time delays in class, at least ones like this. I was just reading your post and think I got a just of it, Is there a nice way to make it adjustable?

Kevin
 
Maybe I am thinking to simple but....

Couldn't you do this using a TON timer and a TOF timer.

Example:

Input is high, start TON (let's call it "OutputStart") and TOF (we'll call it "OutputStop")

OutputStart and OutputStop DN (done) bits turn ON the output.

So, "OutputStart" runs for 1/2 second and then turns ON the Output.

When Input goes low, "OutputStop" continues to run for 1/2 second.

Too simple?
 

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