Double coil syndrome ..need Clarification.

I m just learning and no industrial experiance...Please explain the concepts...


-----------| I:0.1 |--------------------( O:0.0 )-----
|
|
-----------| I:0.2 |--------------------( O:0.0 )-----
|
|
-----------| I:0.3 |--------------------( O:0.0 )-----

Micrologix 1000..

3 diffrent inputs-toggle- (XIC) and 3 output having same address!!!!

Online--- 1 and 2 input buttons are not working ..and 3 input is working...

My concept ...

On scanning first read all inputs and made the input datatable.if input 1 is true ..it condradicts with 2 nd rung..so not showing output..but why the third ring says no problem.??? even though after the last rung output update scanning starts from the begning right??? so it condraticts with first rung..but not happennig and 3rd works....please expalin......

Micrologix 1000..

The last one wins...

The address O:0.0 is just a memory location. The logic is scanned from top to bottom, so the address O:0.0 is written three times.

Then, at the end of hte scan, the contents of the address O:0.0 is written to the output point. It is only then that the real output changes states...to match whatever was written to it in the last rung in which it was used.

but after the last scan of output ..plc again scans and updates right??/So then there will be a contradiction ???

No, the output point is only updated during the housekeeping between scans. The last rung will always win.

This is not the case with Controllogix, where the outputs are updated asynchronous to the PLC scan.

But in a Micrologix, the last one will always "win"...

An important point is that the status of the contacts when viewed from a programming package is the status at the point of the communication which is after the full scan of the ladder. So again the status of all occurances of O:0.0 as viewed online, in your example, would be the status as set by the last rung. They would not be the status at the end of each individual rung.

you are NOT alone in your confusion ...

for a step-by-step explanation, read the following post – and pay particular attention to the paragraph that starts: "Elaborating on Step 2" ...

http://www.plctalk.net/qanda/showthread.php?postid=7448#post7448

from the way that you've phrased your question, it sounds like you are suffering from the very common misconception that the OTE "INSTRUCTION" on the ladder rung is/represents/controls the actual output device in the field ... secret handshake: it does NOT do that ... instead it controls the "bit" (the "BOX") located inside the PLC processor's memory ...

suggestion:

watch the 11 videos linked from the "Sample Lessons" page of my website ... watch them IN ORDER and see if that helps you understand ...

going further:

you can also learn a great deal of what goes on "under the hood" of the PLC by working through the "Email Quizzes" on my website ... you'll find a link to them on the same "Sample Lessons" page that I mentioned above ...

I hope this helps ...

Try this example

Check out this explanation of you question posted by member Ron Beaufort on his site. This will give you a better understanding of the concept of the scan cycle, and why the results are not as expected.

http://www.ronbeaufort.com/sample_lessons.htm

Also, think about what the code you have is really saying. You obviously want the output to be controlled by all three inputs. But how would the PLC know what to do with diferent combinations of the inputs being true?

I see I have been the slowest once again.........

:site:

I see I have been the slowest once again.........

Click to expand...

ah, but the "reinforcement" is a good thing ... and I certainly appreciate the reference ...

OkiePC said:

No, the output point is only updated during the housekeeping between scans. The last rung will always win.

This is not the case with Controllogix, where the outputs are updated asynchronous to the PLC scan.

But in a Micrologix, the last one will always "win"...

Click to expand...

So what would the output be for contrologix processors?

in the simplest "plain vanilla" situation, a double coil in a ControlLogix system can cause the output to "flicker" or "flash" ...

the "last coil" will USUALLY win, because the contents of the output bit/boxes are USUALLY sent to the output modules at the end of each task ... this means that the status of the "last" OTE has a much better chance of being sent than the status of the "first" OTE ...

now here's the part that makes the ControlLogix act differently from the PLC-5, the SLC-500, and the MicroLogix systems ...

since it is also possible to send the contents of the bit/boxes to the output modules at ANY point during the ladder logic execution, then there is a small "window of opportunity" for the status of the first OTE to be sent ...

just remember that the "flicker" or the "flash" will be VERY brief and in many cases you won't be able to see the output change ... (for example, an incandescent lamp might not have time for its filament to heat up or cool off) ... so ... if you're going to experiment with this type of effect, it's best to use a sizeable relay/contactor as the output device ... that's because the armature of the relay will have a certain amount of physical inertia – which can make a "clicking" sound even though the change in the output is very brief ...

anticipating your next question:

let's look at the same "double coil" syndrome in a COMPACT-Logix (not CONTROL-Logix) system ...

in the simplest "plain vanilla" situation, a double coil in a CompactLogix system can also cause the output to "flicker" or "flash" ...

but the "last rung will USUALLY win" idea doesn't quite fit in this situation ... here it's more of a random tossup of which "coil" will win ...

here's the reason ...

with local I/O in a COMPACT-Logix system, the contents of the output bit/boxes are NOT sent to the output modules at the end of each task ... this means that the status of EITHER of the OTEs has roughly an equal chance of being sent ...

but ...

here's where it can get tricky ...

suppose that the ladder logic program is LONG – but the two "double coil" OTEs are located very near each other ... that means that the "window of opportunity" for the status of the first OTE to be sent is very small – when compared to the chance for the status of the last OTE to be sent ... in this case, the last OTE will USUALLY prevail ...

still - all things being equal – in most cases you'll still get a lot more "flicker" or "flash" from a double coil setup in a COMPACT-Logix system when compared to an identically programmed CONTROL-Logix system ...

going further ...

if you're really into this type of thing, you should experiment with different settings for the RPI (Requested Packet Interval) and notice how that can also affect the operation of the system ...

or ...

just avoid any and all exposure to "double coils" and get on with your life ...

(unfortunately we don't always get a chance to pick our own battles – and occasionally a double-coil will end up on our doorstep through no fault of our own) ...