Addressing first bit of a timers accumulator?

I'm working on a small project to learn some more PLC programming, and I've come across a small problem.

Before I mention the problem itself (aside from the title) I'll give you guys a quick background so you have a better idea of how muh I know.

I've been programming computers off and on as a hobby since I was about 14 (tried when I was 12 and quickly gave up). I'm 21 now, and I'm in my second year of college (though on my first co-op placement, because I didnt find one last year).

Coming from a programming background,I understand a lot of what I'm doing with PLCs, and I'm really just trying to learn how to convert my knowledge of programming languages into programming a PLC. (I end up making a lot of state diagrams and such.)

Anyway, here's what I'm doing with the project:
I need to have 4 push button inputs, that must be pressed in a specific order (1-2-3-4). If an incorrect button is pressed (including repeting a previous button), or the sequence is not input within 3 seconds, the "incorrect" light quickly flashes for 3 seconds, and then the program resets itself. If the correct buttons are pressed within 3 seconds, the "correct" light flashes.

I've got most of it coded, but I've run into a snag in the way I had planned on programmning the light flashing. I'm using a timer set to every .2 seconds, trigger a counter, and swap the status of a light (the light is latched or unlatched depending on what state it is in). I'm trying to watch the counter to see whether the bit 0 of it's accumulator is a 1 or a 0 to decide which state the light should be in (essentially using a mod 2 counter).

I'm currently being told I must specify the address to the bit level...

I'll attach the .rss file, so you guys can take a look (and give me any pointers on how to better do stuff, or tings that might not work as intended)

C5:0.ACC\0 should get you where you need to go.

Keith

Ahh, such a short answer to a long post :/

Regardless, thanks for the help, I'm still learning a lot about how things work exactly in RSLogix, so the odd thing about addressing and such confuses me at times. I can usually figure out what's going on, but I'm going off the (rather weak) help files in the program, and my own knowledge from reading other programs, and such.

Any other hints on how I could do things better, or things I should maybe try to avoid in the program?

I have a personal issue with latched based state machines. There really is nothing wrong with them; it's just a personal thing. I think integer based state machines are easier to deal with and more descriptive. Think a CASE-SWITCH construct in C.

Also, the way your code is currently written you will get the incorrect sequence bit set every time the button is pressed. AB PLC programs scan top to bottom, left to right. Taking your first button press, Correct Latch 1 will be set on the press and will be true when the next branch in that rung is executed.

Keith

Even after adding the "/0" to the C5:0.acc bits, there are many things in the program that don't seem to be working as intended.

You shouldn't have two timers with the same address--especially when they have different input/timing conditions. You may also want to add a condition to start the 3 second timer on the first button press or something. As it is now, if the PLC runs for 3 seconds, it's too late to start pressing buttons.

As kamenges stated, your incorrect sequence bit will always be set.

Nothing seems to flash--the counter never seems to make it past 1 in the accumulator.

You may want to go through the code and add comments describing what should be happening as each rung executes.

Do you have a PLC or emulation software to test the code?

I see what your saying.

I'm using latches because I'm following the directions of an assignment. Long story short, I've got access to some assignments from the first PLC programming course for my program (or at least old ones), and happen to be working on the first advanced lab (which is the hardest project in there).

What all would I need to do to move from a latch based state machine to an integer based one?

As for the first rung, I decided to add a timer on another branch below the incorrect sequence check. Now when I press the first button, it'll latch Correct Sequence 1, and start a timer, with the branch above the timer requiring the timer to have started before it will become true, making it necessary to have pressed the button once before that branch is possible.

I then modified the rest of the rungs in the input section to have the XIC moved inside the area under the branch, and added an XIO checking if the previous button's correct sequence bit is set. this way I explicitly set the correct or incorrect sequence depending on the previous button's bit.

In making this modification, the timer is perfectly fine sitting in the first rung at the end opf the branch, because the only time that timer even matters is if they press the first button in correct sequence. If they hit any other button it immediately goes into the "incorrect sequence" mode anyway.

EDIT: Just noticed that this does not stop someone from pressing a button twice in a row. Making the top part of a branch require the bottom part to be met first would effectively only trigger after the first press of the button, correct?

This may be a good time to look up the oneshot (OSR) instruction. you could fix the issue I brought up by transposing your branches and putting a oneshot after the input condition.

The general concept behind integer state machines is you move a state number to state variable as you transition from state to state. So in your case you would replace the latches with MOV instructions and the contact from the latch bits with EQU or NEQ instructions as required.

As I said there is nothing wrong with the latch method. I just find the state value method easier to implement and follow.

Keith

Well, I don't have much trouble understanding the latch method, at least in this size of project. I've seen some of the larger projects at the company I'm working as a co-op student, and they have a good approach. (They use the 5 rung logic method, more or less.)

Also, looks like I missed that last post (I was probably in the middle of composing my previous post when you posted that). I've fixed some stuff up from what I had it before. I can upload the .rss again if you want (with comments, if need be).

And no, I don't have anything to emulate this on, I'm simply thinkin things through as much as I can without using my brain as a surrogate emulator :/ Like I said, I come from a computer programming background, so I'm working mostly on trying to convert the computer programming concepts into workable ladder logic. What gets me the most is trying to implement If-Then-Else logic, which I'm so used to dealing with.

upload the .rss so we can look at what you have

Well, when I was trying to wire things up for this, I decided that It'd be best just to rewrite from scratch. If I've got time sometime soon, I'll try rewriting it, and post that.