RS500 Double integer ?

Jeff23spl

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Jan 2010
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Is there a way to use a double integer in RS500

I need to count a long data and would like to save it on a 32 bits sized bloc

I was using a float but a 32 bits integer would give me more lenght?
 
Please specify the exact CPU model. That is what controls the ability to have double integer ('long' in the SLC500/Micrologix lines) not RSLogix 500.
 
i just read about long word with a 1200 in another thread but i'm using an old SLC 5/05 1747L553 and didn't find where i can add a longword in data table...Is it because slc doesn't support it ?
 
Float are limited about number of digits so having a too long word will flush detailed info....VS a double integer that will keep them...


.. up to the limitation that a double has. While integer types have limits at their end points (smallest/largest) floats have internal (my term) limitations also (number of significant digits).

And my version of RSLogix 500 does not show double integer (long) capability for the SLC processors.

In my world integer and float aren't equal ???

And a bit isn't equal to a float either. Yet the bit can hold definite information. The data types are tools and we must respect their limitations.
 
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You can do 32 bit math in a 5/05, but you must manipulate the carry and overflow bits with extra logic.

If you are incrementing the value by 1 each time (count) then it is not too hard to do this:

RSLogix500 Help said:
Math Overflow Selected S:2/14
Set this bit to 1 when you intend to use 32-bit addition and subtraction.

When this bit is set and the result of an ADD, SUB, MUL, or DIV instruction cannot be represented in the destination address (underflow or overflow): the overflow bit is set S:0/1, the overflow trap bit is set S:5/0, and the destination address contains the unsigned truncated least significant 16 bits of the result.

When this bit is reset (default) and the result of an ADD, SUB, MUL, or DIV instruction cannot be represented in the destination address (underflow or overflow): the overflow bit is set S:0/1, the overflow trap bit is set S:5/0, and the destination address contains 32767 if the result is positive or -32768 if the result is negative.

Overflow Trap S:5/0
When this bit is set (1) by the controller, it indicates that a mathematical overflow has occurred in the ladder program.

Carry S:0/0
This bit is set (1) by the controller if a mathematical carry or borrow is generated. Otherwise the bit remains cleared.

Overflow S:0/1
This bit is set (1) by the controller when the result of a mathematical operation does not fit in its destination. Otherwise the bit remains cleared.

Zero Bit S:0/2
This bit is set (1) by the controller when the result of math or data handling instructions is zero.

Sign Bit S:0/3
This bit is set (1) by the controller when the result of math or data handling instructions is negative.


Math Register (32 bit ) S:14-S:13
Use this double register to produce 32-bit signed divide and multiply operations, precision divide or double divide operations, and 5-digit BCD conversions. These two words are used in conjunction with the MUL, DIV, DDV, FRD, and TOD math instruction. The math register value is assessed upon execution of the instruction and remains valid until the next MUL, DIV, DDV, FRD, or TOD instruction is executed in the user program.
 
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When using a float for a large integer the float will have a practical resolution limitation of 2^24-1, or 16,777,215. Beyond that value a float can no longer be used to substitute for an integer.

The SLC 5/05 supports a 32 bit math register but using it can be somewhat cumbersome.

Any 16 bit processor can be made to do 32 bit math if you properly manage overflow and carry bits. In the SLC it gets a little more interesting if you are doing anything besides addition, but you can find algorithms for doing 32 bit math with 16 bit words on the internet.

edit to add: I think there are also some technotes in the AB knowledgebase showing to to do unsigned math and long math on the 16 bit processors.
 
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maybe it's just me.. but I take the simple way.

I use 2 or even 3 integer files for larger numbers.

add 1 to item1..when reaches 999 increment item2 - zero item1
add 1 to item3 when item2 reaches 999 - zero item2
zero item3,item2, item1 when item3 it reaches it goal

gives me 3 integer files. item3,item2,item1 (999,999,999)

just gotta display it right :)

keep adding integers to get to the largest digit you want.

now this makes calculations with that number kinda odd. btw. but it can be done.
 
maybe it's just me.. but I take the simple way.

I use 2 or even 3 integer files for larger numbers.

add 1 to item1..when reaches 999 increment item2 - zero item1
add 1 to item3 when item2 reaches 999 - zero item2
zero item3,item2, item1 when item3 it reaches it goal

gives me 3 integer files. item3,item2,item1 (999,999,999)

just gotta display it right :)

keep adding integers to get to the largest digit you want.

now this makes calculations with that number kinda odd. btw. but it can be done.

This has been the method I have used most often.
 
I would never use the 999 technique

I have always added 16 bit values and used the carry bit to extend precision. 2^32=4294967296 which has a range much greater than 999,999,999. Also, the 32 bit accumulator can be divided directly. On a SLC5xx the 32 bit number can be loaded into the special 32 bit register and do a divide using the DDV (I believe) instruction.

It is easy to multiply 16x32 or 32x32 bit numbers in a 8 or 16 bit micro. A 16x32 bit multiply requires two multiplies and the results of the two multiples must be added together to get a 48 bit result.

I can even divide 48 bits by 16 bits on a micro-controller. It is more difficult or to do on a PLC because PLCS are crippled.

PLCs should support both signed and unsigned math.
I would have gone into this years ago but it became irrelevant with the advent of 32bit PLCs. Today you should simply buy a more powerful PLC and avoid the hassle.
 

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