ladder logic question - race conditions?

Hello,
I need to answer this ladder logic question, but I dont understand how the race conditions work. Can anyone explain how the outputs update themselves for each scan?

Here is the question:

Are the addresses physical outputs or are they internal bits? What PLC are we pretending to use?

I'm not 100% certain if these questions matter for other PLC models, but I'm pretty much exclusively trained on Allen Bradley. Outputs only update at the end of each scan (not including special instructions). Bits update "real time" so to speak.

So as you go through, each address will update as you read left to right, top to bottom.

Like in the case of A = 1. You see XIO B is true, because B hasn't turned on yet. C turns on. Then the next output branch, B turns on. So B and C are currently on. Then the next rung, C is on, D is off, so D turns on. End of scan 1, B, C, and D, are all on.

Second scan, XIC A is true, but B is on so XIO B is false, so C turns off. B is on, C is off, and D remains on, because XIO C is true and XIC D is true.

Then continue in a similar manner.

This looks like something out of Ron Beuafords web site. If it is not I believe he discusses the same concept and actually makes it make sense.

Dan Bentler

Thank you Tharon,
I believe this is for general plc scan rate understanding. What I couldn't understand is that the logic is updated by the output conditions on each scan.

So to continue with your logic is this correct?:

........ A B C D
scan0 0 0 0 0
scan1 1 1 1 1
scan2 1 1 0 1
scan3 0 0 0 0
scan4 0 0 0 0
scan5 1 1 1 1
scan6 1 1 0 1
scan7 0 0 0 0

rastapapa said:

Thank you Tharon,
So to continue with your logic is this correct?:

........ A B C D
scan0 0 0 0 0
scan1 1 1 1 1
scan2 1 1 0 1
scan3 0 0 0 0
scan4 0 0 0 0
scan5 1 1 1 1
scan6 1 1 0 1
scan7 0 0 0 0

Click to expand...

I did not get that when I did it. My Scan 3 is different than yours.

At scan 3, A goes off. So the logic in rung 1 makes B and C turn off. But what about the second rung? D was on previously, and wasn't shut off anywhere. So D remains on. XIO C is true, XIC D is true, so D is on.

Scan 3 0 0 0 1

Try again from there.

Edit:
This is what I got as the answer, I'm fairly confident that I'm right, but there's always a small chance I could be wrong. Colors have been changed to hide the lines (you should only be able to see them if you highlight it with your mouse). Try it yourself and see if I'm right or you are right.

........ A B C D
scan0 0 0 0 0
scan1 1 1 1 1
scan2 1 1 0 1
scan3 0 0 0 1
scan4 0 0 0 1
scan5 1 1 1 0
scan6 1 1 0 0
scan7 0 0 0 0

oh right, good catch:

How does this look:

........ A B C D
scan0 0 0 0 0
scan1 1 1 1 1
scan2 1 1 0 1
scan3 0 0 0 1
scan4 0 0 0 1
scan5 1 1 1 1
scan6 1 1 0 0
scan7 0 0 0 0

Scan 5 has an error.

Now that you understand the flow of the logic, do you understand what this program has accomplished?

The program doesn't have a specific outcome, but what I don't understand is why the logic in scan 5 is updated for rung 2. Shouldn't that happen in scan 6?

rastapapa said:

The program doesn't have a specific outcome, but what I don't understand is why the logic in scan 5 is updated for rung 2. Shouldn't that happen in scan 6?

Click to expand...

Scan 5 starts, reaches rung one and says that now, C is On. So now, still during scan 5, D is on, and C is on. Scan 5 reaches rung 2, and now both conditions are false, and D is turned off. So at the end of Scan 5, A is on, B is on, C is on, and D is off.

And the program does have a specific purpose. It has created a Flip-Flop for D. Every time input A turns on, D changes states. 0 to 1, 1 to 0, etc.

C is a "one shot" generated by input A. C is true for one scan when A goes 0 to 1. D toggles between 0 and 1 every time C goes true.

If you expand the given truth table, you will notice the pattern in the logic. It repeats itself.

I have a tiny bit of confusion left in me only because of the way C is updated in scan 2 by the means of the B XIO bit. I think that the only reason I can see why C is not turned off by that B XIO bit during scan 1 -- similar to the way D turns off in scan 5--because in scan 1 B's XIO bit is in a higher location compaeed to where B is Set, therefore, the XIO bit cant be set until the next scan (true?).

In other words, in scan 5, D is able to be shut off because C's XIC bit is examined in rung 2 after if is changed in rung 1.

Is my understanding correct?

Thanks again!!

Once the program reaches an output rung (or branch), it does the logic based on what ever is true prior to that output rung. And the bits are updated then. When it reaches the next rung, it uses all the updated info it has so far from the previous output rungs (and branches).

So in this case, the status of C is updated first every scan. Then B, Then D.

So yes, your understanding is correct. In Scan 1, the XIO B is true because it hasn't reached the OTE B that comes later in the program. In Scan 2, the XIO B is false because Scan 1 has processed the OTE B. Similar events happen in rung 2 during scan 5. C is updated before reaching rung 2, and when you look at rung 2, the new states of C are used.

I know you are in school but a warning. This is how this logic structure would be scanned in many PLCs.

But there are some (DirectLogic) in which the ladder as shown is an illegal construct and others (Modicon) in which the scan is top to bottom a column at a time yielding a totally different analysis.

Just don't lock your thoughts that this analysis is true for absolutely every PLC.

Thank you all. I didnt understand the scan logic and you have helped me greatly!!!

Sorry if this topic was considered answered or closed!

I hope I don't sound intrusive, but this is really interesting.
Considering the fact that I have just started learning the basics of Ladder Diagram (LD) and how logic flows from top to bottom and left to right, I would like to point out my understanding.

From my solving of this LD:

A B C D
-------------
S0 0 0 0 0
S1 1 1 1 1
S2 1 1 0 1
S3 0 0 0 1
S4 0 0 0 1
S5 1 1 1 0
S6 1 1 0 0
S7 0 0 0 0
S8 0 0 0 0

I just added S8 to complete the flow.

The aim of this example is show that the output D is in fact a race.

Reason: S1 & S5 have the exact same values for A, B & C but opposite values for D, in S1, D=1 and in S5 D=0
and similarly for S2 & S6 , S3 & S7 and S4 & S8

I would really appreciate if some one could validate and second my reasoning.

Thanks!

bernie_carlton said:

I know you are in school but a warning. This is how this logic structure would be scanned in many PLCs.

But there are some (DirectLogic) in which the ladder as shown is an illegal construct and others (Modicon) in which the scan is top to bottom a column at a time yielding a totally different analysis.

Just don't lock your thoughts that this analysis is true for absolutely every PLC.

Click to expand...

I remember a question in my plc & scada exam about program flow and remember arguing it out with the teacher during the semester about how what he was teaching was dated and that it is dependant on plc vendor, but during my exam I answered the question as the teacher would have incase I got it wrong so i'm with you Bernie!