RS500 branching

Narlin

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Mar 2010
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As a relative newcomer, I was surprised to find that i was limited to 4 "nested" output branches in RS500 ladder logic. OK, for sometime now i have worked around that without any real issues. However, in reading code from others (a great way to learn), i came across about 50+ output branches on a single rung - well, it turns out that they were "parallel" branches - like whose to know? Anyway - can someone please explain the difference between these types? I haven't gotten myself in trouble yet, but i suppose it could happen. I am guessing there might be some difference in execution sequence? I didn't find anything in the pdf manuals.

narlin
 
When a branch is made it "remembers" the logical truth of the point where it starts on the left. When it's a parallel branch the 'truth status' is the same as the branch above it. Use a new/nested branch when you can't use the parallel, like after a contact on the branch above, because it has to "remember" a possibly different 'truth status'. This calls for stacks of information and whatnot. Stacks tend to be limited. The parallel just keeps "remembering" the same state as the start of the branch above. No additional 'stack' space is needed.

This is all supposition from doing machine language programing but it seems to explain the difference. Also the "upside-down wedding cake" just looks ugly to my eyes.

Are you having any trouble in entering the parallel branch as opposed to a new branch?
 
The explanation concerning stacks is reasonable, but i don't quite understand the nested truth sequence. Are you saying that the T/F outcome of the rung above a nested rung effects the nested rung? I haven't tried this yet in code. If i can, i would like to find a simple example that would show a different output for nested vs parallel branching.

narlin
 
I just went to try this in LogixPro (its quik), and curiously, one can only make parallel branches there! No upside down wedding cakes.
narlin
 
Yes you want to avoid nested branching (unless you need instructions on some of the branches) and just use extended branches (right click on a corner and "Extend Branch" Up/Down).

You can also drag and drop branches to "fix" upside down Devo Hats too.

If you double click to the left of a rung with nested branches you can see the extra BST and BND instructions (waste of memory) as compared to the same rung with extended branches.
 
The code i was reviewing had many parallel output branches on a single rung. Indeed the purpose of the rung was to examine a large number of alarm conditions and each of the parallel outputs has one XIC or Compare instruction and one -(L)- bit latch. It wouldn't have been different to have had an equal number of individual rungs and i think they were simply grouped this way for reader continuity.

However, i don't understand yet how to assemble some nested rungs that would/could give a different result from parallel ones.

narlin
 
They wouldn't be different. But the nested/new branch uses a whole new stack space for the "remembered truth". That's where the limitation comes in.



----+-----] [------------( )---+
|'A' 'B' |
+-----]\[----+-------( )---+
| | |
| +--] [--( )---+
| |
+-----] [------------( )---+
| |
+-----]\[------------( )---+



The first branch is a 'new/nested' and remembers the status at 'A' by using the stack. The next branch is also a 'nested' branch and remembers the - possibly different - truth status as it exists at 'B' on the next place on the stack. (When this branch evaluation finishes it releases its place on the stack.) The next branch is a parallel and inherits the same 'truth' that 'A' "remembered". The final is also a parallel branch and again inherits the same 'truth' that 'A' holds. This final parallel branch releases the stack position that was picked up in 'A'. (Note: this is my interpretation, I don't design AB PLCs.)
 
Bernie,
I see the construct difference and understand the reason why nesting might be needed. Unfortunately, allen bradley (unlike KOYO for example) doesn't allow me to see the assembled code. To truly figure out what the PLC is doing, i am going to have to devise some testing. This sounds a bit like a Ron question.

I will come back here and post the answer if any. You may have hit on it that there will never be a difference in the outputs since the use of a nested branch is impossible to simulate with parallel structure when nesting is actually needed. The remainder of the time (nested not required) they would be the same//

narlin
 
Narlin said:
Unfortunately, allen bradley (unlike KOYO for example) doesn't allow me to see the assembled code. To truly figure out what the PLC is doing, i am going to have to devise some testing.

If you double click on the left side of the rung, you can see the mnemonic representation of the code which will reveal the exact order that it will be processed by the PLC/SLC.

Narlin said:
I will come back here and post the answer if any.

Answer to what question? I am unclear what you are questioning. If it's the execution sequence, without any contacts, there's no difference. You can copy/paste and modify a rung and compare mnemonics to see the execution order.
 
Bernie's explanation piqued my interest on what would happen differently on nested vs parrellel branches. I was interested if a 3 branch rung with the bit above as an xic to the bit below latching would behave differently because of stack updates. Mainly I was curious if it would take a scan in between each branch latch because of the stack updating or not. I ran it in a SLC with a ONS control bit on the rung and both ways (nested and parrelled) worked the same all bits latched on the first scan.
 
"If you double click on the left side of the rung, you can see the mnemonic representation of the code which will reveal the exact order that it will be processed by the PLC/SLC."

OH! Is that what that pop up is? OK, that makes testing virtually unnecessary. I had seen that before and always been in too much of a hurry to investigate.

narlin
 
"If you double click on the left side of the rung, you can see the mnemonic representation of the code which will reveal the exact order that it will be processed by the PLC/SLC."

OH! Is that what that pop up is? OK, that makes testing virtually unnecessary. I had seen that before and always been in too much of a hurry to investigate.

narlin

You can also enter logic using the mnemonics, which is my preferred way of programming. In 5000, you can just start typing at the beginning of a rung or branch. I think in 5 and 500 you have to doubleclick, but I can't remember, it's been so long.
 
You can also enter logic using the mnemonics, which is my preferred way of programming.


Me too. It would kill my patience to have to drag and drop instructions.

I had a vender for one of the minor PLC brands stop in one day... Asked me if I would consider using there products. This was one of the things that I asked him about. He didn't understand, so I showed him how much faster it was to program that way. He didn't have much to say after that.

The other thing, that he had to contend with, is local support. It makes a big difference, if I have a card go bad, that I have a new one in town, without having to stock it myself.
 

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