The anti-reset windup bit in the configuration word establishes how the PID function's integrator behaves while the CV is clamped at minimum or maximum value.
When the bit is zero and the CV is clamped the function adjusts the integral component as necessary to maintain the CV at the clamped value. This means that the CV will remain at the clamped value until the error changes sign because as the magnitude of the error changes the function will adjust the integral contribution to the CV to maintain the CV. In this mode, when you make a large change to the SP, you will find the PV reaches the SP faster, but there probably be an overshoot.
When the bit is set to 1 and the CV is clamped, the function will freeze the integral contribution to the CV at its value when the clamp was applied. When the magnitude of the error decreases to the point where the CV falls back within the lower and upper clamp limits, the integrator will resume calculating. In this mode, when you make a large change to the SP, you will find that there is less of an overshoot when the PV reaches the new SP, but it will take longer to get there.