First Scan Bit in ControlLogix

dcooper33

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Jun 2011
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Hi guys,
I've got a basic question about how the "S:FS" bit is handled in CLX processors.
I'm wanting to trigger some anti-diameter reset logic on power-ups on an unwind stand which is controlled by an L61 processor.
The routine where the diameter reset is controlled is in a periodic task which runs every 30ms. What I'm unsure about is if the processor will scan every routine on the first scan, or only the continuous ones. Therefore would an XIC S:FS instruction evaluate false by the time my periodic task is called?
If this is the case, then I can do something like this instead:

Code:
SOR BST XIO Always_True_Unwind_1 OTE First_Scan_Unwind
NXB OTE Always_True_Unwind_1 BND EOR
I'd prefer to use the S:FS bit if possible, it's less rungs, and cleaner in my opinion. I've got quite a few machines that I need to roll this out on. Anybody test this one out before?

Thanks, guys.

Cheers,
Dustin
 
That is an interesting question to which I do not know the correct answer.

If you have a main task which is continuous, you could latch an internal global bit:
XIC S:FS OTL My1stScanBit
And, then only unlatch it after your last usage of said bit in the periodic task. If more than one periodic task may need access, you may want to latch a unique bit for each of them to be certain that they each have proof that a first scan took place.

Using the OTL rather than sealing in the OTE will remove the need for branches making it only slightly simpler than what (i think) you have coded above. I expect one of the Logix gurus will come along and provide a definitive answer, for all of us, pertaining to the root question.
 

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