dcooper33
Lifetime Supporting Member + Moderator
Hi guys,
I've got a basic question about how the "S:FS" bit is handled in CLX processors.
I'm wanting to trigger some anti-diameter reset logic on power-ups on an unwind stand which is controlled by an L61 processor.
The routine where the diameter reset is controlled is in a periodic task which runs every 30ms. What I'm unsure about is if the processor will scan every routine on the first scan, or only the continuous ones. Therefore would an XIC S:FS instruction evaluate false by the time my periodic task is called?
If this is the case, then I can do something like this instead:
I'd prefer to use the S:FS bit if possible, it's less rungs, and cleaner in my opinion. I've got quite a few machines that I need to roll this out on. Anybody test this one out before?
Thanks, guys.
Cheers,
Dustin
I've got a basic question about how the "S:FS" bit is handled in CLX processors.
I'm wanting to trigger some anti-diameter reset logic on power-ups on an unwind stand which is controlled by an L61 processor.
The routine where the diameter reset is controlled is in a periodic task which runs every 30ms. What I'm unsure about is if the processor will scan every routine on the first scan, or only the continuous ones. Therefore would an XIC S:FS instruction evaluate false by the time my periodic task is called?
If this is the case, then I can do something like this instead:
Code:
SOR BST XIO Always_True_Unwind_1 OTE First_Scan_Unwind
NXB OTE Always_True_Unwind_1 BND EOR
Thanks, guys.
Cheers,
Dustin