Ashwin
Member
I have a question concerning logic on the AB CLX. I have been posting so often these days, guess a lot of people know what i am upto.
ANYWAYS....
My algorithm is split into two peices, one in ladder and the other using FBD. My program is supposed to converge and its a iterative process, so a timer basically waits till the end of a process and clears up all values and the system is ready to crunch new values(the new values are a result of the number crunching the algorithm produces)
The whole issue concerns some Function blocks and the fact that the outputs dont seem to follow the inputs. Like for example, I have a GRT block( same holds true if i use LES etc), I kill the inputs to the block at the end of the timing cycle, including the Enable IN pin but my output stays a ONE as the states dont get updated.
In other words the Enable OUTPUTS stay latched!! despite my inputs to a block being ZERO.
So i am currently ending up with a race condition.
Does anyone have any suggesstions? I have previously tried to replicate what i did in FBD in Ladder and it works well. The only issue with that is i have almost 40 pages of code written in FBD.
What is the best way to clear outputs in FBD at the end of a cycle? The inputs to the source A and source B and the enable In are all forced to zero through Ladder. how can I make the output go to zero?
Makes me think, why cant AB provide users with an option to keep EN OUT latched or otherwise. I mean we have an option to latch bits or leave them a high in ladder. Why cant they add that feature in FB? Anyways, that doesnot bother me at this point of time.
Ashwin.
ANYWAYS....
My algorithm is split into two peices, one in ladder and the other using FBD. My program is supposed to converge and its a iterative process, so a timer basically waits till the end of a process and clears up all values and the system is ready to crunch new values(the new values are a result of the number crunching the algorithm produces)
The whole issue concerns some Function blocks and the fact that the outputs dont seem to follow the inputs. Like for example, I have a GRT block( same holds true if i use LES etc), I kill the inputs to the block at the end of the timing cycle, including the Enable IN pin but my output stays a ONE as the states dont get updated.
In other words the Enable OUTPUTS stay latched!! despite my inputs to a block being ZERO.
So i am currently ending up with a race condition.
Does anyone have any suggesstions? I have previously tried to replicate what i did in FBD in Ladder and it works well. The only issue with that is i have almost 40 pages of code written in FBD.
What is the best way to clear outputs in FBD at the end of a cycle? The inputs to the source A and source B and the enable In are all forced to zero through Ladder. how can I make the output go to zero?
Makes me think, why cant AB provide users with an option to keep EN OUT latched or otherwise. I mean we have an option to latch bits or leave them a high in ladder. Why cant they add that feature in FB? Anyways, that doesnot bother me at this point of time.
Ashwin.