David Hugg
Member
My colleague and I are having a problem with the use of a PIDE algorithm with external anti-reset windup (ARWU) active. We are using a ControlLogix PLC running the RSLogix 5000 software.
The PIDE algorithm outputs a digital signal to some switchgear that can impose clamps on the signal. The clamped signal is output from the switchgear as an analog value. This analog value is converted back to a digital signal, which is sent to the PIDE algorithm as CVPrevious. We set the flag CVSetPrevious to force the PIDE to use this external signal as the ARWU value.
It should also be noted that, at the moment, the A/D conversion does not run on a cyclic clock with the PIDE block; that is we cannot guarantee that the A/D conversion runs after the PIDE block at each cycle. Also, the analog signal is a little bit noisy, which will be reflected in the converted digital signal.
When the PIDE block is placed in Auto mode, the output begins to integrate immediately in the positive direction, even if there is zero control error. We first assumed that there might be a problem with the noise introduced by the analog signal. We implemented a low pass filter on the ARWU readback signal. Though a heavy filter (τF = 100s) reduced the rate of integration, the output still integrated in the positive direction over time.
My colleague decided to implement this logic in the RSLogix 5000 simulator, and simulated the presence of the switchgear with a digital dither that is added to the output of the PIDE block. The dither switches between a small positive and equivalent-in-magnitude negative value every other processing cycle. In other words the dither has a zero mean. This modified signal is fed back as the ARWU signal. We were very surprised to find that the same situation occurs when the PIDE block is switched to Automatic; that is the output of the controller integrates in the positive direction, even though we have guaranteed that the “noise” has a zero mean.
We ran this purely digital signal through the same low pass filter, and once again observed that, although the rate of integration was reduced, we still see the output integrating in the positive direction.
We now believe that the error we are observing may be due to the asynchronous processing of the PIDE and A/D blocks. However we also cannot discount the possibility that there may be an error in the PIDE block with regard to the handling of the CVPrevious input. We can modify the logic to have it all run on a single cycle in our simulation, however implementing this change on the real process would require a total shutdown, which we are not anxious to do.
Has anyone else encountered this issue? If so, how did you go about rectifying the problem?
The PIDE algorithm outputs a digital signal to some switchgear that can impose clamps on the signal. The clamped signal is output from the switchgear as an analog value. This analog value is converted back to a digital signal, which is sent to the PIDE algorithm as CVPrevious. We set the flag CVSetPrevious to force the PIDE to use this external signal as the ARWU value.
It should also be noted that, at the moment, the A/D conversion does not run on a cyclic clock with the PIDE block; that is we cannot guarantee that the A/D conversion runs after the PIDE block at each cycle. Also, the analog signal is a little bit noisy, which will be reflected in the converted digital signal.
When the PIDE block is placed in Auto mode, the output begins to integrate immediately in the positive direction, even if there is zero control error. We first assumed that there might be a problem with the noise introduced by the analog signal. We implemented a low pass filter on the ARWU readback signal. Though a heavy filter (τF = 100s) reduced the rate of integration, the output still integrated in the positive direction over time.
My colleague decided to implement this logic in the RSLogix 5000 simulator, and simulated the presence of the switchgear with a digital dither that is added to the output of the PIDE block. The dither switches between a small positive and equivalent-in-magnitude negative value every other processing cycle. In other words the dither has a zero mean. This modified signal is fed back as the ARWU signal. We were very surprised to find that the same situation occurs when the PIDE block is switched to Automatic; that is the output of the controller integrates in the positive direction, even though we have guaranteed that the “noise” has a zero mean.
We ran this purely digital signal through the same low pass filter, and once again observed that, although the rate of integration was reduced, we still see the output integrating in the positive direction.
We now believe that the error we are observing may be due to the asynchronous processing of the PIDE and A/D blocks. However we also cannot discount the possibility that there may be an error in the PIDE block with regard to the handling of the CVPrevious input. We can modify the logic to have it all run on a single cycle in our simulation, however implementing this change on the real process would require a total shutdown, which we are not anxious to do.
Has anyone else encountered this issue? If so, how did you go about rectifying the problem?
