Hi, Unusual Request. I need a line of code / method that I can use to fault a 1756-L72 Contrologix Processor. Was going to do a divide by zero but I'm told that this processor can cope with that. Reason is for SAT, need to prove relationship/response with other external hardware if the processor faults.
Thanks.
You are misinformed about "divide by zero" causing a processor fault, it, alone, doesn't.
And let us be clear that the following only applies to SLC/MicroLogix processors. It is the
only range of processors that have this "capability".
When an instruction executes that causes a math overflow, the Overflow
status bit is turned on, and another status bit called the "Overflow Trap" bit is also set. Nothing can "unset" this trap bit automatically, even if the next, or subsequent math instructions don't cause an overflow, so it will remain turned on for the rest of the program scan.
In some sort of unfathomable design thinking, they made it so that if the "Overflow Trap" bit is set at the end of the program scan, the controller will "major fault".
This is about as much use as a chocolate teapot, your program has crashed out, and you have absolutely no idea where in the scan (i.e. which instruction) caused it.
If an instruction causes a math overflow, and it is important to you, then you must write code to inspect the math status flags after each instruction that could cause overflow, and deal with it there and then.
Every single SLC/MicroLogix program I have ever seen has an unconditional rung as the last rung of program file 2, which simply unlatches the "Overflow Trap" bit, S:5/0. At the end of the scan, it is too late to do anything about a math overflow condition, it will most likely have already wreaked its damage....
