What effects the status word in Siemens S7?

Hi, I'm trying to decipher some Statement List code written for a Siemens S7-300 in the late '90s. I've come across an AN instruction, which I understand performs an AND NOT operation with the RLO bit from the status word. What I'm wondering is what are all the things that could effect the state of the RLO bit? Is it just comparison instructions, like <I and ==I, or are there others? Can shift operations shift bits into the status word like in x86 assembly? Thanks for any help you can give me!

Are you using Simatic manager to view/decipher the code - if so click on an instruction then press F1 to get the help on that instruction. The help will tell you if it affects the RLO. I've not seen a list of instructions the specifically affect the RLO

I looked at the help files and they helped a little bit, but they also raised more questions for me. For instance, I'm looking at the following piece of code:


For the first AN statement, what does the bit DB88.DBX201.0 get NANDed with? According to the help documentation, "AN checks whether the state of the addressed bit is '0', and ANDs the test result with the RLO". So apparently it doesn't perform the NAND operation on the bit itself, but on a bit that is the result of a test for whether or not the bit is 0? And why does the help doc say it ANDs the test result instead of NANDing the result (this is an AND NOT operation after all). Also, where is the result of this operation stored?

Sorry for all the (possibly stupid) questions, but this doesn't seem to work the way I expected a NAND to work, and the documentation hasn't been very helpful IMO.

It is buried in the help,

/FC First Check Bit (Status Word, Bit 0)

The /FC bit signal state controls a logic operation string.

The /FC bit is status word bit 0.

Each logic operation queries the /FC bit signal state and the addressed contact.

· If the /FC bit signal state equals ‘’1,’’ an instruction logically combines the result of its signal state check on its addressed contact with the RLO generated since the first check and stores the result in the RLO bit.

· If the /FC bit signal state equals ‘’0,’’ the logic string begins with a first check.

The logic string ends and the /FC bit is set to ‘’0’’ with the assignment of a value (S,R,=) or with a RLO-dependent jump instruction.

There is no NAND, AN could be written as "A with the inverted state of the operand"

Hopefully the ladder equivilent will makes thing clear.

Thanks for the ladder diagram, it is very helpful. I may have been thinking about this all wrong. Let me see if I've got this straight now: let's say that initially,

DB88.DBX201.0 =0
DB88.DBX203.0 =1
DB88.DBX231.0 =0
/FC = 0

The first AN operation checks /FC and, seeing that it is 0, sets it to 1. It then ANDs /FC with 1 (the inverse of DB88.DBX201.0). The result of this operation is 1, and that is stored in RLO. The second AN checks /FC and, seeing that it is 1, ANDs RLO with with 0 (the inverse of DB88.DBX203.0) and stores the result (0) in RLO. The third AN comes along and checks /FC and, seeing that it is still 1, ANDs RLO with 1 (the inverse of DB88.DBX231.0) and stores that result (0) in RLO. Once an assignment or an RLO-dependent jump is executed, /FC resets to 0 so that a future logic operation knows that it is the first one.

Am I getting this right?

Spot on.