Ron Beaufort
Lifetime Supporting Member
extract from a post on another forum ...
first of all ... RSLogix500 has a nifty series of troubleshooting tools: “Test Single Scan”, “Test Single Step”, and “Run to Rung” which would make it a lot easier to experiment and find out exactly how things like the Done bit of the ACB instruction operate ...
but unfortunately these excellent tools are not available for the smaller MicroLogix processors ... and so to the question: is there a way to “freeze frame” the processor’s scan in a “lab” environment to help analyze tricky “what-happens-when” type questions? ... the answer: yes, there is ...
[attachment]
here we’ve set up a very simple test program with the code that we want to analyze located in a subroutine ... whenever we want to execute the subject code for just ONE scan, we simply toggle the “trigger bit” to an ON condition ... the processor will then execute the JSR, run through the subroutine file, and then return to Ladder File #2, where it will immediately turn OFF the “trigger bit” ... the subroutine has just been scanned for ONE and ONLY ONE pass ... now we can go back at our leisure and examine the condition of the “flag” bits which we’ve installed in the subroutine ... when we’re ready for the next single step, we reset the “flag bits” and then fire the “trigger bit” again ... by systematically manipulating the input data that the instruction operates on, and then examining how the processor sets and resets the instruction’s status bits, we can gain a DETAILED knowledge of exactly what’s going on in our program ... and in many cases we can go well beyond what the official book has to say about a particular subject ...
once you’ve seen how this technique works, the only limitation to its use is likely to be your imagination ... I’ve been using it successfully for several years to debug programs which have defied all other methods of analysis ...
PS ... for those who want to follow the original post on the other forum, you can find it:
here
first of all ... RSLogix500 has a nifty series of troubleshooting tools: “Test Single Scan”, “Test Single Step”, and “Run to Rung” which would make it a lot easier to experiment and find out exactly how things like the Done bit of the ACB instruction operate ...
but unfortunately these excellent tools are not available for the smaller MicroLogix processors ... and so to the question: is there a way to “freeze frame” the processor’s scan in a “lab” environment to help analyze tricky “what-happens-when” type questions? ... the answer: yes, there is ...
[attachment]
here we’ve set up a very simple test program with the code that we want to analyze located in a subroutine ... whenever we want to execute the subject code for just ONE scan, we simply toggle the “trigger bit” to an ON condition ... the processor will then execute the JSR, run through the subroutine file, and then return to Ladder File #2, where it will immediately turn OFF the “trigger bit” ... the subroutine has just been scanned for ONE and ONLY ONE pass ... now we can go back at our leisure and examine the condition of the “flag” bits which we’ve installed in the subroutine ... when we’re ready for the next single step, we reset the “flag bits” and then fire the “trigger bit” again ... by systematically manipulating the input data that the instruction operates on, and then examining how the processor sets and resets the instruction’s status bits, we can gain a DETAILED knowledge of exactly what’s going on in our program ... and in many cases we can go well beyond what the official book has to say about a particular subject ...
once you’ve seen how this technique works, the only limitation to its use is likely to be your imagination ... I’ve been using it successfully for several years to debug programs which have defied all other methods of analysis ...
PS ... for those who want to follow the original post on the other forum, you can find it:
here
Last edited:
