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Search: Posts Made By: drbitboy
Forum: LIVE PLC Questions And Answers January 17th, 2020, 09:19 AM
Replies: 41
Views: 2,791
Posted By drbitboy
Thanks everyone!

Thanks everyone!
Forum: LIVE PLC Questions And Answers January 15th, 2020, 10:38 AM
Replies: 41
Views: 2,791
Posted By drbitboy
Thank you! I finally snagged one cheap off of...

Thank you! I finally snagged one cheap off of eBay, but it will not be here until next week. You may think I am asking stupid questions now... ;)

The -32768 16-bit INTEGER result suggests the...
Forum: LIVE PLC Questions And Answers January 14th, 2020, 06:30 AM
Replies: 41
Views: 2,791
Posted By drbitboy
The result is -32768 unless the [Math Overflow...

The result is -32768 unless the [Math Overflow Selected] status bit (S:2/14?) is latched; see the first-pass rung of the example (http://www.plctalk.net/qanda/showpost.php?p=836878&postcount=25).
...
Forum: LIVE PLC Questions And Answers January 14th, 2020, 06:25 AM
Replies: 41
Views: 2,791
Posted By drbitboy
Thank you!

Thank you!
Forum: LIVE PLC Questions And Answers January 13th, 2020, 06:57 AM
Replies: 41
Views: 2,791
Posted By drbitboy
Holy cow!

Hahaha, I cannot believe this: the same thing happens in [RSLogix Emulate500] with 32-long LONGs i.e. I lose the low-order bits in some cases when a 32-bit MULtiply overflows!
...
Forum: LIVE PLC Questions And Answers January 7th, 2020, 10:22 AM
Replies: 41
Views: 2,791
Posted By drbitboy
Wink And the beat goes on

Okay, I had some fun with you in the previous post, but the bold italics bit above is flat-out wrong; so I am highlighting that for any poor soul who stumbles onto this thread in the future.

In...
Forum: LIVE PLC Questions And Answers January 7th, 2020, 09:01 AM
Replies: 41
Views: 2,791
Posted By drbitboy
Wink The thread that would not die

I can assure you that I am not in the least bit;) confused, as I have lived down in the weeds (bits) of integers and reals of multitudinous* complexions, denominations, persuasions and stripes for...
Forum: LIVE PLC Questions And Answers January 6th, 2020, 09:14 PM
Replies: 41
Views: 2,791
Posted By drbitboy
Wink yes, I know, I was referring how many significant...

yes, I know, I was referring how many significant bits can be in the final value, not the zero-based position of the MSBit.

After all, I am drbitboy ;).
Forum: LIVE PLC Questions And Answers January 6th, 2020, 08:04 PM
Replies: 41
Views: 2,791
Posted By drbitboy
That was wrong, it can get to 32 bits.

That was wrong, it can get to 32 bits.
Forum: LIVE PLC Questions And Answers January 6th, 2020, 12:21 PM
Replies: 41
Views: 2,791
Posted By drbitboy
Actually, as Mike Nash suggested, it does...

Actually, as Mike Nash suggested, it does probably pass the 16-bit INTEGER arguments to be multiplied, but

it passes them as 32-bit REALs,
the 32-bit REAL product result only keeps at most the...
Forum: LIVE PLC Questions And Answers January 6th, 2020, 12:09 PM
Replies: 41
Views: 2,791
Posted By drbitboy
The help file for [RSLogix Micro Starter Lite]...

The help file for [RSLogix Micro Starter Lite] makes the identical claim for MicroLogix i.e. if the [Math Overflow Selected] (S:2/14) bit is set, then any overflow will result in the truncated result...
Forum: LIVE PLC Questions And Answers January 6th, 2020, 10:11 AM
Replies: 41
Views: 2,791
Posted By drbitboy
Stale phart thread

Mike Nash solved this issue in the first response, yet this thread hangs around like a stale phart; I apologize for bringing it up.

JesperMP: Go back to the original post of this thread: no...
Forum: LIVE PLC Questions And Answers January 5th, 2020, 09:37 PM
Replies: 41
Views: 2,791
Posted By drbitboy
Thank you, but that does not help because the...

Thank you, but that does not help because the problem is a bug in the emulator. I have already implemented the workaround: use LONGs instead of INTEGERs.
Forum: LIVE PLC Questions And Answers January 5th, 2020, 04:20 PM
Replies: 41
Views: 2,791
Posted By drbitboy
Yes, well, my slide rule that my Dad gave me is...

Yes, well, my slide rule that my Dad gave me is over 22" long*, so if we are going to start unzipping and measuring ... ;)

The point of the original post is that the program WAS using INTEGERs in...
Forum: LIVE PLC Questions And Answers January 5th, 2020, 04:11 PM
Replies: 41
Views: 2,791
Posted By drbitboy
The original calculation used only integers, no...

The original calculation used only integers, no mixing, but the result was off: the MUL of two ODD 16-bit INTEGERs was an EVEN INTEGER product.

The problem appears to be that it is not the...
Forum: LIVE PLC Questions And Answers January 2nd, 2020, 05:45 PM
Replies: 41
Views: 2,791
Posted By drbitboy
Test case

I emulated Mike Nash's suggestion, that the bits are being lost in a floating-point multiply, here (https://github.com/drbitboy/plc_rng/blob/master/verify/03.f).:bonkhead:

The results are...
Forum: LIVE PLC Questions And Answers January 1st, 2020, 02:14 PM
Replies: 41
Views: 2,791
Posted By drbitboy
It matters very much

If we do a [Bitwise-inclusive AND] with -410032571 and 32767 (i.e. FFFFH) to get the lower 16 bits of the answer, we get the correct 16-bit result i.e. 26181, which is what I expect a non-emulated...
Forum: LIVE PLC Questions And Answers January 1st, 2020, 02:07 PM
Replies: 41
Views: 2,791
Posted By drbitboy
Thumbs up I'll bet you're right. I suspect the real,...

I'll bet you're right.

I suspect the real, non-emulated MicroLogix hardware doesn't do this.

Thanks.
Forum: LIVE PLC Questions And Answers January 1st, 2020, 12:30 AM
Replies: 41
Views: 2,791
Posted By drbitboy
Question Are wild MUL results a known bug, or is ML Emulate simply not to be trusted?

Windows 10, x86_64,
RSLogix Micro Starter Lite
RSLogix Emulate 500 6.00.00.07 (CPR9)
RSLinx Classic 2.57.00.14 CPR 9 SR 3

See the attached ZIP: the result of a MUL instruction on 16-bit...
Showing results 1 to 19 of 19

 
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