View Single Post
Old February 20th, 2018, 11:34 AM   #27
Lifetime Supporting Member + Moderator
United Kingdom

daba is offline
daba's Avatar
Join Date: Jul 2004
Location: uk
Posts: 4,513
Originally Posted by GaryS View Post
......The way to prevent it from faulting the processor id in very last line of the ladder code unlatch the math overflow bit.
Or you can at every line in the ladder that dos a math function the next line should be to unlatch the math overflow bit.
It is the Math Overflow Trap bit you have to unlatch S:5/0, not the Math Overflow Status bit, S:0/1.

Unlatching it after every instruction that affects the math status bits is a bit overkill, IMHO, and will probably "break" most projects I've seen in terms of extended scan times, and the additional memory required.

Although it a cheap and nasty "trick", there's always a potential that the overflow trap bit could get set again in an STI or DII that fires off at precisely the wrong moment (just after the OTU and before the END rung). And do not get confused with the STI and DII "Overflow" bits, these are badly named - I would prefer they were called "Overlap" bits.

My best advice is to find what causes the overflow (or underflow), and fix the real problem, not just mask it.
ControlLogix & SLC Training
a-b train ltd.
tel: 07506 73 9999
nil illegitimi carborundem

  Reply With Quote