Control Logix/studio5000, is there a way to write a force instruction?

In studio 5000, is there a way to write a force mask into a rung?

Long story short, I would like to create a test routine for a FAT test. In this, I would like to be able to individually set certain inputs high for certain conditions. As well as prove that all DI, DO, AI etc are functioning. This is to assist in the fact that what is being built here is only half the story and more inputs from devices that dont exist here are needed to satisfy this. Aside from building an entirely separate PLC setup with ins/outs or other type of microcontroller, I want to find an easy way to make this work.

I know there is not a force instruction, but I want something that works likes that. Where I can just point to the device(s), give a mask, and it does the rest.

Thanks Folks

If you map your inputs to individual bits, and place them in there own routine. You can stop scanning that routine and then toggle the bit states as needed. This was standard at one of my former employers, mad FAT testing, much easier.

As Ken stated, it is common to map h/w to internal tags. I see aliasing rarely if at all.

Forgot to mention, this is with SIL2 components using the sil2 AOI for IF16 and IB32.

Because of this, the inputs are mapped to the SIL2 and decisions are made there that would stop me from writing to the bits that have been individualized. Basically, I have to force at the module. I have yet to try skirting around the SIL2... as this is kind of crucial to the whole shebang.

to add more information... 2 IB32s are one in the eyes of the logic. Both must agree or it faults on the channel that didn't agree and it faults the module pair.
1. sil2 pair of modules for inputs with 1492-taifm/tifm interface boards
2. redundant control chassis with RM2, controllers, en2trs.

That should help spell out a little more information as to why I am doing things this way.

1.0 said:

Forgot to mention, this is with SIL2 components using the sil2 AOI for IF16 and IB32.

Because of this, the inputs are mapped to the SIL2 and decisions are made there that would stop me from writing to the bits that have been individualized. Basically, I have to force at the module. I have yet to try skirting around the SIL2... as this is kind of crucial to the whole shebang.

Click to expand...

I map to internals in the safety task, can still do the same thing there. You won't have any luck forcing at the module level.

What I do for testing is branch to a XIC Test_Bit.


Toggle that bit on or off to test.


Sometimes instead of calling them test bit I call them Force or Enable and leave them in after testing

Not sure what your AOI does and if logic in the rest of the program references stuff done in the AOI or back to the hardware tags... you can map the required forceable bits in the rungs after the AOI and the rest of the program will use the forced logic instead of the AOI mapped logic.

If the logic inside the AOI is the problem, then perhaps look at COP the field IO into an internal tag with the same data structure and hopefully this can be recognized into the AOI, with force rungs located before the AOI

If all of the program logic directly references the hardware tags then you're out to lunch as these asynchronously update on modern processors in the middle of logic scans and cannot be confirmed to be in forced state for the whole program scan.

Be cautious when troubleshooting whatever path comes out of this forcing bits, as trending logic most times won't catch multiple state changes within a single scan giving problems with grey areas for actual cause.