Memory Clock Edge Generator

[PL] mk

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Join Date
Apr 2017
Location
src
Posts
16
I'm not got at STL and I have a little problem.
I want to create FB generating edges for PLC memory clock timer. On FB inputs you just have to assign the integer value for memory clock address and byte number where do you want to have the edge from memory clock.

Problem is with creating coil from edge.
When I detect the timer state using stat memory called "edge" the "mc" bit (in example bit 0.5) is transfer to "mce" and "mce" bit acts like "mc" - like a normal memory clock bit.
When I assign M memory bit to detect edge, everything works correctly - bit 5 on "mce" is an edge signal.
Can somebody tell me where the problem is?
Oh...in addition when I use the stat memory to detect this edge I recive "Area length error when writing".

VAR_INPUT
mc : INT ;
mce : INT ;
END_VAR
VAR
edge : BOOL ;
END_VAR

Code:
L     #mc                         // in my case 5
SLW   3
LAR1  

L     #mce                       // in my case 265
SLW   3
LAR2  

A     M [AR1,P#0.5]        //m5.5 address
FP    M    266.0             //in this case everything works
//      FP    #edge         //in this case I recive are legnth error when writing
=     M [AR2,P#0.5]

Diagnostic buffer:
Code:
Event 1 of 10:  Event ID 16# 2523
Area length error when writing
Instance DB, bit access, Access address:    269
FB number:      3
Module address:     22
Requested OB: Programming error OB (OB121)
Priority class:  1
Internal error, Incoming event
10:00:24.601 AM  04/30/2017
(Coding: 16# 2523  0179  8E05  010D  0003  0016)
 
AR2 is used inside of FB-blocks. You modify AR2 value to 265. On your FP call of stat variable "edge" points now to AR2 + Offset, which block have maded on start. (I Assume that edge have address 4.0 on stat configuration so after AR2 modification CPU search edge from P#265 +P#4.0 (269) instead of P#0.0+P#4.0)

If you want use AR2 register, you need save and load its value on start and end of your own change. Also AR2 manipulation needs to move different place.


https://support.industry.siemens.co...iables-after-saving-the-block-?dti=0&lc=en-WW

http://s7tools.com/index.php?option...n-block-fb&catid=17:tips-and-tricks&Itemid=30

http://s7tools.com/index.php?option=com_content&view=article&id=22%3Afb-call-qbehind-the-scenesq-&catid=17%3Atips-and-tricks&Itemid=30



You can modify your code only to use AR1 register or use Dword variables instead.




L #mc // in my case 5
SLW 3
T #index1 //stat variable index1 (Dword)



L #mce // in my case 265
SLW 3
T #index2 ////stat variable index2 (Dword)



L #index1
L P#0.5 // or maybe L L#5?
T index1_and_bit

L #index2
L P#0.5 // or maybe L L#5?
T index2_and_bit



A M [index1_and_bit] //m5.5 address
// FP #edge // edge
= M [index2_and_bit] //M265.5 address



 
Last edited:
You were right with the address shift after AR2 modification.
Anyway. I corrected the code according to your suggestion and now it works fine.
The question is whether such a programing have any sense?
It's hard to find such signals, and anyone who is not familiar with the program can use this address area and disturbed program functionality.

Code:
      L     #mc                         // in my case 5
      SLW   3
      T     #index1

      L     #mce                        // in my case 265
      SLW   3
      T     #index2

//Prepare memory clock address
      L     #index1
      L     P#0.0
      +D    
      T     #MClock0

      L     #index1
      L     P#0.1
      +D    
      T     #MClock1

      L     #index1
      L     P#0.2
      +D    
      T     #MClock2

      L     #index1
      L     P#0.3
      +D    
      T     #MClock3


      L     #index1
      L     P#0.4
      +D    
      T     #MClock4


      L     #index1
      L     P#0.5
      +D    
      T     #MClock5

      L     #index1
      L     P#0.6
      +D    
      T     #MClock6

      L     #index1
      L     P#0.7
      +D    
      T     #MClock7


//Prepare memory clock edge address
      L     #index2
      L     P#0.0
      +D    
      T     #MClockEdge0

      L     #index2
      L     P#0.1
      +D    
      T     #MClockEdge1

      L     #index2
      L     P#0.2
      +D    
      T     #MClockEdge2

      L     #index2
      L     P#0.3
      +D    
      T     #MClockEdge3

      L     #index2
      L     P#0.4
      +D    
      T     #MClockEdge4

      L     #index2
      L     P#0.5
      +D    
      T     #MClockEdge5

      L     #index2
      L     P#0.6
      +D    
      T     #MClockEdge6

      L     #index2
      L     P#0.7
      +D    
      T     #MClockEdge7



//Generate edge
      A     M [#MClock0]
      FP    #sEdge[0]
      =     M [#MClockEdge0]

      A     M [#MClock1]
      FP    #sEdge[1]
      =     M [#MClockEdge1]

      A     M [#MClock2]
      FP    #sEdge[2]
      =     M [#MClockEdge2]

      A     M [#MClock3]
      FP    #sEdge[3]
      =     M [#MClockEdge3]

      A     M [#MClock4]
      FP    #sEdge[4]
      =     M [#MClockEdge4]

      A     M [#MClock5]
      FP    #sEdge[5]
      =     M [#MClockEdge5]

      A     M [#MClock6]
      FP    #sEdge[6]
      =     M [#MClockEdge6]

      A     M [#MClock7]
      FP    #sEdge[7]
      =     M [#MClockEdge7]
 
Before you can use and modify STL and indirect addressing, you need to know lot of what PLC does. You can use AR1 and AR2 if you know what they also do and what can happen when using them inside FB.

You could also use loop on your code, but then it goes more unclear.

You can put AR1 and AR2 inside of FC-block (again save and load registers), Call FC then on FB networks. You FB stays then clean of all indirect addressing.
 
Thinked little bit more. If you want make edges for every bit of byte and save edges to different area, then it would be easiest without indirect addressing:

"oneshotbyte" := "sourcebyte" AND NOT "membyte" ;
"membyte" := "sourcebyte" ;

http://www.plctalk.net/qanda/showthread.php?t=76887

That way everyone also see where bits are writed. (From cross reference or Search/Go to (Overlapping access to memory areas selected).
I would use memory marker area for this, so that you can have symbol name for byte and individual bits.
 

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