Positive edge in SCL all byte

Lukasz_Poland

Member
L
Join Date
Aug 2019
Location
Poland
Posts
28
Hello


I have got a problem with positive edge from "system clock memory byte" in Tia Portal. I would like to change byte"system clock memory" to another byte but it should be "positive edge byte"
I saw that function with XOW and AW but it was in STL language and I dont know how to write it in SCL.



Sorry for my poor English.
 
Could you post the STL version, I can convert to SCL for you.

I think I understand what you need, but an example would clarify it.
 
Code in STL:
L MB 0
L MB 100
XOW
AW
T MB 1
L MB 0
T MB 100
In MB 100 I have all positive edges from system clock.
That code I was trying convert to SCL.
 
Yes, exactly.
I want achieve positive edges in byte MB100. I dont know how convert my attached STL code to SCL. I tried bud it didnt work.
 
Lukasz_Poland said:
Yes, exactly.
I want achieve positive edges in byte MB100. I dont know how convert my attached STL code to SCL. I tried bud it didnt work.
Click to expand...


Show your code (screen shot via [Prnt/Sys Req], past into [Paint], save as PNG, attach via
attach.gif
button in [Go Advanced] posting tool in this thread; also show your [System Clock and Memory] window that @Rob... mentioned.
 
Dear Colleagues


Everything works fine.Sorry for the confusion and thank you again for your quick reply and written code.I have a lot of work and study ahead of me.


Thank you again.
 
Actually, that code does not work: see the red-circles in the image below.

That said, it is close to working and the fix is trivial.
Untitled.png​
 

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