Positive edge in SCL all byte

Lukasz_Poland said:
In my plc is something like that. Could you tell me where is the problem?
Click to expand...


Yes, because we need to think about digital PLCs as being devices that change over time.


The problem is that our code (your code, my code, perhaps @Rob...'s code*) uses the expression [mb0] (%MB0) in two separate lines of code, and the evaluated result of that expression [mb0] can change between the execution of those two lines.

Consider these three lines, executed across two scans:


[Scan 1, line N]         oneshotbits := (last_scans_mb0 XOR mb0) AND mb0;

[Scan 1, line N+1]       last_scans_mb0 := mb0;

[... finish Scan 1 ...]

[... start Scan 2 ...]

[Scan 2, line N]         oneshotbits := (last_scans_mb0 XOR mb0) AND mb0;


​
  • If a bit in mb0 is 0 at the time of [Scan 1, line N],
    • then its corresponding bit in [oneshotbits] will be 0,
  • BUT if that bit in mb0 changes over the next few microseonds to 1 before the evaluation of [Scan 1, line N+1],
    • then the value of the corresponding bit in last_scans_mb0 will be 1!
  • And so, at [Scan 2, line N],
    • that bit will be 1 in BOTH [last_scans_mb0] and [mb0],
      • and the the XOR will evaluate to 0 for that bit
The solution is straightforward; do you see it?

P.S. Siemens makes the more or less the same mistake in the evaluation of the .Q bit of its IEC timer object for TOFs an TONs.

* @Rob...'s example code in Post #4 used [ew0] for the value of mb0, so he may have already fixed the problem.
 
Last edited:
drbitboys code suggestion is fine.

All you need to do is to assign suitable symbols to suitable addresses.
MB0 is the clock byte.
MB1 is often also used for system bits.
So anything from MB2 and up is fine, only be sure that the address is not already in use, and does not overlap with other addresses.

If for example oneshotbits = MB10, then check that MW9, MW10, MD7, MD8, MD9 and MD10 are not already used. I include the uneven addresses just in case someone hasn't learned to stay on even addresses.
 
Dear Colleagues


Thanks for the explanation.
I will download the code(MB0 move to another adress) to plc and check the traces again.

The program that I am writing is to be for the CIP tank cleaning station. I have another question. If I write this program, will you look and judge its correctness? I care about your professional opinions and comments (what to improve, change ...).

I try to write the program with comments in English.
 
drbitboy said:
Yes, because we need to think about digital PLCs as being devices that change over time.


The problem is that our code (your code, my code, perhaps @Rob...'s code*) uses the expression [mb0] (%MB0) in two separate lines of code, and the evaluated result of that expression [mb0] can change between the execution of those two lines.

Consider these three lines, executed across two scans:


[Scan 1, line N]         oneshotbits := (last_scans_mb0 XOR mb0) AND mb0;

[Scan 1, line N+1]       last_scans_mb0 := mb0;

[... finish Scan 1 ...]

[... start Scan 2 ...]

[Scan 2, line N]         oneshotbits := (last_scans_mb0 XOR mb0) AND mb0;


​
  • If a bit in mb0 is 0 at the time of [Scan 1, line N],
    • then its corresponding bit in [oneshotbits] will be 0,
  • BUT if that bit in mb0 changes over the next few microseonds to 1 before the evaluation of [Scan 1, line N+1],
    • then the value of the corresponding bit in last_scans_mb0 will be 1!
  • And so, at [Scan 2, line N],
    • that bit will be 1 in BOTH [last_scans_mb0] and [mb0],
      • and the the XOR will evaluate to 0 for that bit
The solution is straightforward; do you see it?

P.S. Siemens makes the more or less the same mistake in the evaluation of the .Q bit of its IEC timer object for TOFs an TONs.

* @Rob...'s example code in Post #4 used [ew0] for the value of mb0, so he may have already fixed the problem.
Click to expand...


Its true, but Siemens uses MB and MW syncronously. I/O can be asyncronous depending how it is readed/writed on PLC or iis it reded from process map or directly from cards on older platform.
Clock bytes are ayncronous as L D stated and probles is there. Still you can copy clock bytes on seperate MB on first network of code and then use these syncronously on whole program.
 
Last edited:
Lukasz_Poland said:
Hello


I have got a problem with positive edge from "system clock memory byte" in Tia Portal. I would like to change byte"system clock memory" to another byte but it should be "positive edge byte"
I saw that function with XOW and AW but it was in STL language and I dont know how to write it in SCL.



Sorry for my poor English.
Click to expand...


Is there any particular reason why it must be SCL coding?

You can write ladder or FBD on separate networks between SCL networks.
 
Not sure of the device he is using, but the S7-1200s don't support STL.

So I assume, he's used this function before or has it in an older project and needed to convert to a modern CPU.
 

Similar Topics

mosama
Step7 Detecting Positive Edge In SCL
Dear all, What is the name of the function used for positive edge detection in Step7 SCL ?? Thank you
Replies
8
Views
13,030
mosama
mosama
L
Positive edge detection in SCL (S7)
Does edge detection instruction exist in SCL or I have to write it myself? Can it be done like this? if x and not x_old then //code end_if...
2
Replies
17
Views
28,334
Terry Woods
T
A
S7-1200 / TIA V13 positive edge true but no output
Can anyone see why i am not getting an output on this? it is detecting a rising edge and saying that it is true but going any further to the...
Replies
5
Views
2,395
RClem
RClem
J
Positive Signal Edge Bit not working
I am using Portal for the first time and I am simply trying to do a one shot. My code wasn't working so I made a new network with all new tags so...
Replies
7
Views
2,491
mk42
M
M
Positive edge contact
Hello, I wish everyone the best for the new year. I am working with FATEK and winproladder. I want to build a project that has 8 DI and 1 DO. At...
Replies
2
Views
2,816
manin
M
Back
Top Bottom