the plc might have complementary racks.
one rack will be inputs and the other will be outputs.
That is a misleading statement - "one rack will be inputs and the other will be outputs.".
You can mix I and O in each rack, so long as you
complement them, i.e. where you have I at one address in one chassis, you must place an O in the other, or vice-versa, or leave one of the slots empty.
Complementing I/O to another rack is a similar technique to complementing I/O within a single rack when using 2-slot addressing (where 2 physical slots have the same Group address). This will only work for uni-directional I/O modules (eg. Digital In or Out). Higher level modules )eg. Analog In or Out), require both the I and O images at that address to control the Block Transfer mechanism for the Bi-Directional data transfers.
Complementing the I/O, whether this is done within the chassis using 2-slot addressing with 16-bit modules, or 1-slot addressing with 32-bit modules, or between chassis, will maximise the I/O capability of the processor, which has fixed size I/O image tables, depending on the model. There is a 16-bit word in each table for each R/G/S (Rack/Group/Slot) that the PLC5 variant can handle. Obviously without this "complementary" nature, 50% of each table would be unusable, halving the I/O capability of the processor.
Complementary chassis I/O is unlikely. In 22 years of working on AB systems, I have never come across an installation that used it. I'm not saying
no-one uses it, it can get you out of a hole if you run out of rack addresses and can save you having to swap out the PLC5 to a model with larger I/O capability.
Back to the OP. Yes you can have inputs and outputs at the same logical address. The physical location of those I/O modules is most likely to be in the same module group in one rack, and could be 16-bit or 32-bit modules, depends on the addressing method configured. Less likely the I and O are in different racks, using complementary chassis.
As has been said before, a "must-have" is the rack dip-switch settings to determine the addressing mode.