Challenge - Set Dominate Latch, initially 0 - RSLogix5000

BillRobinson

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Join Date
Oct 2006
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Sydney, Nova Scotia
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OK PLC'ers

Here's the challenge

Create an equivalent Set Dominate Latch, in RSLogix 5000, where the initial output is 0. You can use only function blocks.

By set dominate I mean a latching function which sets the output to 1 when both the set and reset values are 1.

There is already a Set Dominate Latch function block in RSLogix 5000; however, its initial output is 1.

I spent a long time trying to do this, the only way I found to do this is to write piece of structured text code.
 
I presume you want a "Reset Dominant Latch", such that if both "Set" and "Reset" are held true, the "Reset" dominates and turns the output False.

If so, can't you use the existing "Set Dominant Latch" FB, and invert the output.

You will also need to wire the "Set" condition to the FB's "Reset" input, and the "Reset" condition to the FB's "Set" input.

As I don't do much (if any) FB programming, this is a stab in the dark, but I can't see why it wouldn't work
 
Seems the S:FS first scan bit can't be used directly in FBD, so use it in ladder to operate a bool tag and connect that tag to the reset input of the SETD FF (via an OR gate).
 
I presume you want a "Reset Dominant Latch", such that if both "Set" and "Reset" are held true, the "Reset" dominates and turns the output False.
...

OK PLC'ers

Here's the challenge

Create an equivalent Set Dominate Latch, in RSLogix 5000, where the initial output is 0. You can use only function blocks.

By set dominate I mean a latching function which sets the output to 1 when both the set and reset values are 1.

Why presume the OP wants a Reset Dominant Latch when they clearly stated they wanted a Set Dominant. ???? Am I missing something ? It looks to me that you presumed EXACTLY the opposite of what the OP wanted.
 

Well, if I needed to do what the OP wants, that's how I would do it.
OP says he had to develop something in ST to do the task.
Why shag about with a complex solution when a simple one is available.

I fail to see how your suggested solution relates at all to the question.
 
🙃 You are quite correct, Gerry, my apologies for not reading the post through properly. My only mitigating circumstances were - long drive, late night, and too much wine, (hic!).

Surely, though, there must be a way in FB to turn on a bit at the end of the first scan? Then you could use the invert of that bit to assert an OR'd reset on the Set Dominant function, so that its initial state is output false.
 

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