Siemens equivalent for simple 128-bit shift register in RSLogix

Good morning (EST),

I am trying to implement the code below in on an S7-1200. It's barely half a dozen instructions, but I am stuck; I have not even been able to figure out how to conveniently access a bit in a DINT (still searching though; surely it's possible? Yes, and don't call me Shirley ). I'm almost to the point of building an FB equivalent to A-B's BSR instruction.

I'm sure it's just unfamiliarity with TIA and Siemens notation.

If interested, could someone please post TIA LAD code equivalent to the image below, including showing the DB entries. The key behaviors are

• shift register with 128 bits using an array of DINTs (e.g. ARRAY[0..3] of DINT; or UDInts or DWords, or even Bools for that matter)
• on a rising edge of a trigger bit, shift all members of the shift_reg array by 1 bit to the right, cascading bit 0 of shift_reg[N] to bit 31 of shift_reg[N-1] for N > 1
  • and push a zero bit onto shift_reg[3] at bit 31 (128th MSBit)
  • and latch bit of the shift register when some input [bit it] is 1, where I is a non-constant tag with a value between 1 and 127 inclusive.
    
    • bit = bit [I AND 31] of shift_reg[(I AND (-32))/32]; -32 is 16#FFE0 (16-bit signed int)
      [*]So if I is 100, then bit 4 of shift_reg[3]
      
    
    
    
  
  
  [*]output bit 0 of shift_reg[0] continuously
  

Thanks,


Brian Carcich


P.S. this is only for thread https://www.plctalk.net/qanda/showthread.php?t=128167

A bit of a DINT in Data Blocks is adding .%X0 to the DINT address. Otherwise if it's a internal M memory DINT, you can set tags for the bit addresses

Ex: MD0 consists of bytes MB0 MB1 MB2 and MB3. 0 is the most significant, 3 is the least significant. Each byte consists of bits from 7 to 0 (most to least). M0.7 is the most significant bit and M3.0 is the least significant bit of MD0.

I think the AB code is from SLC500 or PLC5, not from Logix.
Maybe because of that, the shift register is cumbersomly arranged into 4 memory cells of 32 bits each in order to get 128 positions.

The AB BSR instruction hides the 4 memory cells (L9:0 .. L9:3).
I think it is a bad idea to try and mimic the AB code with 4 doubleword in the S7 program.
Instead start from scratch with a DB and an Variable as an Array [0..127] of BOOL.
Then the code more or less writes itself.
Can be easily done in LAD, FBD or SCL.

sigmadelta said:

A bit of a DINT in Data Blocks is adding .%X0 to the DINT address. ...

Click to expand...

Thanks.


I apologize for not being clear on the OP.


N.B. I am not using M* memory.


So if I define shift_reg as ARRAY[0..3] of DINT in the DB of an FB, then the LAD syntax for the lowest bit (e.g. for a -|/|-) should be shift_reg[0].%X0? And if bitpos is defined as an INT and has a value between 1 and 127, how do I reference a bit, e.g. shift_reg[3].%X4 when bitpos is 100, using only that INT bitpos?


Also, how do I shift bits across DINT (DWord orboundaries in the ARRAY? It's trivial with masks and bitwise operators, of course, but is there anything more concise that is built-in to the language?

JesperMP said:

...
Instead start from scratch with a DB and an Variable as an Array [0..127] of BOOL.
Then the code more or less writes itself.
Can be easily done in LAD, FBD or SCL.

Click to expand...

Ah, I was wondering about that, but could not get the syntax right. What does the SHR instruction look like with an array of BOOLs? Can you post an image, please? Thanks!

JesperMP said:

I think the AB code is from SLC500 or PLC5, not from Logix. ...

Click to expand...

Yes, MicroLogix actually, but I did refer to it as RSLogix (e.g. 500 or Micro Starter Lite), not just Logix.

There is no instruction in S7 that is exactly same as the BSR in SLC/MicroLogix.
There is an SHR instruction, but it accepts a LONG word size (64 bits) as the biggest variable type.
Personally I would write it in SCL.
A simple FOR loop should do the trick.
i.e.

If you want a canned solution, then I believe the OSCAT library has that.
You can search for it, it is an IEC61131-3 code library that can be imported into TIA.

drbitboy said:

Thanks.


I apologize for not being clear on the OP.


N.B. I am not using M* memory.


So if I define shift_reg as ARRAY[0..3] of DINT in the DB of an FB, then the LAD syntax for the lowest bit (e.g. for a -|/|-) should be shift_reg[0].%X0? And if bitpos is defined as an INT and has a value between 1 and 127, how do I reference a bit, e.g. shift_reg[3].%X4 when bitpos is 100, using only that INT bitpos?


Also, how do I shift bits across DINT (DWord orboundaries in the ARRAY? It's trivial with masks and bitwise operators, of course, but is there anything more concise that is built-in to the language?

Click to expand...

You can count bit index by calculatin


Bit_index/32 = word index
remainder is bit index to dint array.


Then SHR by only one bit


Easier to use serialize (copy from Dint array to array of bits) before Jesper's SCL code.After that desrialize from array of bools to back dints.


Not tested, but serialize and deserialize can copy between different variable types?

JesperMP said:

There is no instruction in S7 that is exactly same as the BSR in SLC/MicroLogix.

Nor like the equivalent BSR in Logix.

There is an SHR instruction, but it accepts a LONG word size (64 bits) as the biggest variable type.

or 32 bits as an upper limit for S7-1200


IF Trigger THEN ...

Wow, a few syntactical changes and that would be valid Fortran (I once converted a Pascal program to Fortran with a series of find-and-replace edits).

Personally I would write it in SCL.


Not an unreasonable statement, but I prefer something concise and efficient (e.g. the RSLogix example in the OP).

Click to expand...

IMNSHO:

• Personally I would rather use a language that had a better instruction set instead of a "much assembly required to do common tasks" sticker.
• Personally I feel like I have an itch on my left ear and Siemens wants me to use my right hand to scratch it, but only by reaching between my legs to get there.
• Perhaps this is why A-B costs more: there is a corresponding savings in programmers' time and reduced program complexity.

I guess instead of asking if anyone one was interested in posting a Siemens LAD version of a simple algorithm, I should have asked if it was even possible to do it simply in Siemens LAD.

Generalised shift left already posted in the thread you are referring to - it's in SCL not ladder though.

L D[AR2 said:

Generalised shift left already posted in the thread you are referring to - it's in SCL not ladder though.

Click to expand...

yah I know, ergo the "much assembly required" wisecrack.


I have tried really hard to get into the TIA and Siemens mindset. And the FB/FC infrastructure has a lot of potential. But I am not sure it is worth it for a small- to mid-size project.

DR: once you get used to it it's great, lost my touch with Siemens but in the 80's & 90's I was an accredited system builder (well the company I worked for), and often was recommended by Siemens as a fluent programmer.
It was & still is a very powerful system, it does require a certain knowledge of a type of assembly type code but what you can do with it is amazing, I once did an experiment where the only Input was referenced as I0.0 This was by loading an MC5 instructions (hex number) from a data block, processing using I think one of the RS instructions to access I/O, not user friendly but would fox many programmers, I also tried to code a simple program instructions in a data block in MC5 code, then run a loop so in effect a small program where the instructions were contained within a range of words, you could also make the code alter in runtime but felt it was too dangerous so never pursued it any further. In fact what most platforms do now is what Siemens have done for probably 40 years, AOI's are the equivalent to function blocks, but in general in those days you either purchased a protected block from them or rolled your own.

Here's the basis for the 128 shift right in ladder:

L D[AR2 said:

Here's the basis for the 128 shift right in ladder:

Click to expand...

yes, thought of putting that into a FB. it does not need the intermediate bBit0Store if the SHRs are interleaved with the {-| |--( )-} rungs.


Sidebar: wow, I went to look at ATT/FIFO (move bits in parallel): is that missing from S7-1200 too? So disappointing.

You can look general functions addon if FIFO isn't on allready on libaries:
https://support.industry.siemens.co...l)-and-simatic-s7-1200-s7-1500?dti=0&lc=en-FI