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Old January 13th, 2022, 10:41 AM   #1
AMarks95
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Logix Designer Element Power Flow Highlighting

Does anybody know if there's a way that I can have Logix Designer apply the green highlight to ALL elements that evaluate true (not just XIO/XIC and OTE) so I can quickly see which elements are being evaluated as true/false (ex. LEQ, GEQ, EQU, NEQ, etc.).

Like so:
EQU Highlight.png

Last edited by AMarks95; January 13th, 2022 at 10:46 AM.
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Old January 13th, 2022, 10:51 AM   #2
drbitboy
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Change request to RA ?

As a workaround, having the EQU drive an OTE on a previous rung, then an XIC on the rung in question instead of the EQU on that rung, would be ugly but do the job.
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Old January 13th, 2022, 10:54 AM   #3
AMarks95
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Quote:
Originally Posted by drbitboy View Post
Change request to RA ?

As a workaround, having the EQU drive an OTE on a previous rung, then an XIC on the rung in question instead of the EQU on that rung, would be ugly but do the job.
Very ugly, and multiply the amount of rungs substantially.
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Old January 13th, 2022, 11:45 AM   #4
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Quote:
Originally Posted by AMarks95 View Post
Very ugly, and multiply the amount of rungs substantially.
Still ugly, but shouldn't add any more rungs, I believe that you can add an OTE after each instruction and it'll still pass through. So if you have GEQ OTE GEQ OTE OTE(Actual output) you would get the green highlighting on the OTEs after the GEQs as an indicator whether or not the instructions are true or false. I haven't tried this, give me a second and I'll see if it works.

EDIT: Seems to work on my 1756-L71 running V24. Again, it's really ugly but would do the trick in a pinch.

Last edited by mylespetro; January 13th, 2022 at 11:48 AM.
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Old January 13th, 2022, 11:46 AM   #5
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Quote:
Originally Posted by mylespetro View Post
Still ugly, but shouldn't add any more rungs, I believe that you can add an OTE after each instruction and it'll still pass through. So if you have GEQ OTE GEQ OTE OTE(Actual output) you would get the green highlighting on the OTEs after the GEQs as an indicator whether or not the instructions are true or false. I haven't tried this, give me a second and I'll see if it works.
That does work.

Not the first time this has been suggested. With the bit instructions all the software has to do is identify if there is a 1 or a 0 to determine if it should be highlighted or not.

The problem with trying to do the same for comparison instructions is that it would require the logic software to perform the logical comparison to determine whether it is true or not. So, we are asking the software to solve the logic just like the PLC controller would. Certainly, something that could be done. But it would probably require more network traffic and usage of the computer CPU. Probably would also considerably slow down on-screen response time.

Ideally the instruction would have had some internal bit that would be a 1 or 0 to identify if it were true or false. Then the software could just examine that bit. But that functionality was never built into these instructions.

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Old January 13th, 2022, 11:47 AM   #6
AMarks95
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Quote:
Originally Posted by mylespetro View Post
Still ugly, but shouldn't add any more rungs, I believe that you can add an OTE after each instruction and it'll still pass through. So if you have GEQ OTE GEQ OTE OTE(Actual output) you would get the green highlighting on the OTEs after the GEQs as an indicator whether or not the instructions are true or false. I haven't tried this, give me a second and I'll see if it works.
That seems like a bit better solution, but possibly skip the OTE after the second GEQ because the actual output OTE would highlight
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Old January 13th, 2022, 11:49 AM   #7
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That seems like a bit better solution, but possibly skip the OTE after the second GEQ because the actual output OTE would highlight
Yeah sorry, I was just using a hypothetical example to show that you can place instructions after an OTE, not referring to your actual screenshot. In other words, the "dummy" OTEs are essentially "short circuits" when it comes to the graphical power flow in the ladder program.

EDIT: Your point stands in my example too actually, I was just pairing each GEQ with a dummy OTE.

Last edited by mylespetro; January 13th, 2022 at 11:52 AM.
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Old January 13th, 2022, 12:02 PM   #8
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Quote:
Originally Posted by AMarks95 View Post
Very ugly, and multiply the amount of rungs substantially.
Agreed, but needs must.

The suggested alternative, to put an OTE of a dummy bit on the same rung right after the EQU (or other compare), I also thought about but ultimately decided against, because it would not work when the input rung of the EQU was false.

One thing I have to keep reminding myself is that most if not all boolean-result instructions are ANDs with their input rung e.g. [XIC bit] is not just <bit?> alone but actually <<input rung?> AND <bit?>?>.

Also note that, in Logix software, that the displayed state of XICs/XIOs/OTEs is based the the state of the bit sampled at some time other than the time of the instruction, and not the the actual result of the instruction, as noted in Ron Beaufort's Most Excellent bootcamp youtube series at this link and demonstrated below:
xxx.png
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Last edited by drbitboy; January 13th, 2022 at 12:17 PM.
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Old January 13th, 2022, 12:24 PM   #9
AMarks95
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Originally Posted by drbitboy View Post
Agreed, but needs must.

The suggested alternative, to put an OTE of a dummy bit on the same rung right after the EQU (or other compare), I also thought about but ultimately decided against, because it would not work when the input rung of the EQU was false.
That would probably be fine as I don't really care what the comparator is evaluated as if it's not actually being evaluated.
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Old January 13th, 2022, 12:35 PM   #10
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Quote:
Originally Posted by drbitboy View Post
...Also note that, in Logix software, that the displayed state of XICs/XIOs/OTEs is based the the state of the bit sampled at some time other than the time of the instruction, and not the the actual result of the instruction...
When I was writing my earlier message I got to thinking, when is the Logix software sampling that bit? Are bits off-screen also being sampled? Does it start sampling when it's on-screen? Are bits off-screen or in a routine that isn't open also being sampled? Because yeah, it is not sampling at the same time the PLC is evaluating.

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