Ladder Execution Order

Does anybody have a good document that explains the Execution Order of "Nested Branches"?

Thanks

If it is in RSLogix double click on the line and a text version of the line will show. You can copy a line and paste it in Notepad to read through it better.


Here is an example of the screenshot:


SOR BST LIM 2 N10:1 18 BST XIC B3:0/11 NXB XIC B3:1/4 NXB XIC B13:5/6 NXB XIC O:5.0/9 NXB XIC O:5.0/10 NXB XIC T4:71/DN BND BST XIO T4:28/DN NXB XIC B13:1/1 BND XIO B3:2/9 NXB XIC B13:2/0 XIC B13:2/15 BND XIC I:2.0/6 XIC I:2.0/2 XIC I:2.0/1 BST XIO I:2.0/3 BST OTE O:4.0/8 NXB OTE B13:0/3 NXB XIO I:2.0/8 TON T4:13 0.01 75 0 NXB TON T4:4 1.0 3 0 BND NXB XIC O:5.0/7 TON T4:18 1.0 25 0 BND EOR

Each branch starts with BST, after a line is processed that is NOT TRUE the NXB calls the next branch. After the last branch, or a line is TRUE there is a BND.


Note that inside a branch there are more BST's for nested branches.


If another BST is encountered after a NOT TRUE line it will skip over the BST's, NXB's and BND's until it finds the NXB or BND for the branch it is in.


In the shown example as soon as it is determined that the first branch is NOT TRUE on both lines the rest of that line is bypassed and the outputs are turned off and the 3 TON timers are reseet.

Is there an official AB document which details this execution optimization?

Knowledgebase article 47165 RSLogix5000 Ladder Programming Parallel Branching, Nesting and Rung Execution Access Level: TechConnect

Thanks, AaBeck. That is exactly what I was looking for!

You're welcome.


I didn't post the KB article link first because a lot of beginners, and others, don't have TechConnect contracts and wouldn't have been able to get it. Being a one-man shop I can't afford one myself and personally think the entire KB database should be available to everyone.


I also think, if the PLC makers want to sell their PLC's they should do what Automation Direct and others do and give the software away, or sell it at a more reasonable price ($45.00 US)


maybe that's just from being an old codger that grew up on 19 cent gasoline, 9 cent candy bars and 10 cent sodas.

Aabeck said:

You're welcome.


I didn't post the KB article link first because a lot of beginners, and others, don't have TechConnect contracts and wouldn't have been able to get it. Being a one-man shop I can't afford one myself and personally think the entire KB database should be available to everyone.


I also think, if the PLC makers want to sell their PLC's they should do what Automation Direct and others do and give the software away, or sell it at a more reasonable price ($45.00 US)

Click to expand...

I agree and I would never voluntarily buy any of their product for that very reason.

Aabeck said:

Each branch starts with BST, after a line is processed that is NOT TRUE the NXB calls the next branch. After the last branch, or a line is TRUE there is a BND.

Click to expand...

Just a small technicality - while your description of the order is correct, the statement above is not quite so.

A branch does not stop scanning or "skip" when it encounters a false instruction. It scans the rest of the branch anyway; it just scans them with a rung-in false condition.

This is especially necessary to understand in Logix-class PLC's (the ones that use Logix 5000/Logix Designer to program, i.e. Compact Logix, Control Logix), because on that platform you can have output instructions mid-branch. Even if your branch contains an AFI (always false instruction), the PLC must still scan all remaining instructions on that branch in case there's a timer that needs resetting, a coil that needs turning off, or a counter that needs it's .CU bit reset to permit a possible count on the next scan. All of these are operations that don't just "happen" - they only occur when the instruction is scanned and executed with a false rung-in condition.


Your example shows an RSLogix 500 program, which does not permit output instructions mid-branch, so it's possible that the above does not apply to your specific example. In SLC's and Micrologix PLC's (and anything else that uses the Logix 5 or Logix 500 platform), output instructions must be placed in parallel at the far right-hand end of the rung. So, I guess it's possible that these processors encounter a false instruction and then skip the rest of the branch, ultimately skipping to the output instructions if need be. I doubt it, but I don't know of a way to prove it one way or the other.

ASF,


Actually a couple years ago I had someone here contest me on "processors encounter a false instruction and then skip the rest of the branch" and I posted the results, and the program, I came up with.



I had to use a SLC5/05 to get the RHC time function and I ran 100 lines with the fist XIC false with a few XIC's then an OTE, recorded the time and ran 100 lines with the false XIC moved to the last XIC of the rung. The results were dramatically different. The first 100 scanned in 19 clicks, the second 100 took 35 clicks.



At least on a SLC when a rung is proved false it jumps to the output(s) without processing any of the other checks. Now, next time I have a CLX on my desk, I am going to find time to test this and see if it is true for the 5K platform.



For a small program it wouldn't make any noticeable difference, but for an automated assembly line keeping this in mind could improve the overall scan time, so I always try to program the most common FALSE conditions first, and have the most common TRUE conditions on the first line of a branch, then work my way to the least common items.

Your point about improving the overall scan time is correct, but your test doesn't necessarily prove your theory.


Again, I've only seen this specifically in relation to the Logix 5000 platform, but if you run the same test on a CLX, you'll get the same results, because the instructions take different times to execute depending on the rung-in condition.


On something like a TON, the difference is not enormous, because it has a number of tasks to do in either case. Changing the state of .EN, .DN, .TT bits, adjusting .ACC registers, etc. But on an XIO or XIC, it's a more clear-cut case of:
Rung-In True: Check state of tag, set rung-out condition based on state of tag and instruction type
Rung-In False: set rung-out false
It doesn't actually have to perform any logic if the rung-in condition is false, so it's much faster to execute. Same with a MOV or a COP or a GRT or a LES or any number of other things.

There's actually a document somewhere on the KB that gives the approximate execution time of each instruction, separated by rung-in condition true and rung-in condition false. It's probably wildly out of date by now, but the long and short of it is, most (or possible all) instructions execute faster if the rung-in condition is false. So, as to your point about scan time - yes, you'll still get faster execution of a given rung if you put the most likely false conditions at the start of the rung, but each instruction on the rung is still being executed. It's just that if your rung goes "false" early on, the remaining instructions take much less time to execute.

Again, can't 100% promise that it's the case for an SLC, but I don't believe that the test you ran proves me wrong. If you wanted to prove me wrong (and I'm happy to be proved wrong, because then I've learned something!), you'd run three tests:

1. 1000 rungs with 10 XIC's on each, followed by an OTE. All XIC's except the last one on each rung are true
2. 1000 rungs with 10 XIC's on each, followed by an OTE. First XIC on each rung is false
3. 1000 rungs with a single, true XIC and a single OTE on each

If I'm right, Test 1 will be fastest, followed by Test 2, followed by Test 3. If you're right, Test 1 will be fastest and Tests 2 & 3 will be identical.

I don't have an SLC handy to test with, but maybe I'll set up my Compact Logix later on and at least prove my theory on that platform

Challenge accepted - I do have a 5/05 on the floor by my desk.


Except I would say Test 1 would take the longest - processing 9 TRUE XIC's then coming to the FALSE one last, where Test 2 would be rung-false after the first XIC.


The real test will be to see if Tests 2 & 3 give different results. But I would change Test 3 to a FALSE XIC just in case turning ON an OTE is different than turning it OFF, might test that too.


Then I need to find a CLX.

Test results:


First, had to cut it down to 500 lines per test because the CPU faulted on ScanTime WatchDog.


Test 3 did not make a difference if the XIC was TRUE or FALSE. Both ways I got 500 rungs at 57 clicks. (Occasionally the clicks jumped upwards to 71, but mostly stayed at 57)


Test 1 with the FALSE at the 10th XIC gave a scan time for 500 rungs of 224, only jumping a few numbers once in a while - staying in the 220's.


Test 2 gave the exact 57 Test 3 did, but for some reason more consistent as it was not jumping up to the 60's or 70's as much as Test 3 did.



Now to find a CLX on eBay....

Just for comparison here is the result for Test 1


I also tried Test 1 turning ALL XIC's TRUE & didn't have a noticeable change in the scan time.

I just ran a few time tests making the rung TRUE up to various points and got the following:


XIC 0 FALSE = 57

XIC 0 TRUE = 76
0,1 TRUE = 95
0-2 TRUE = 113
0-3 TRUE = 132
0-4 TRUE = 151
0-5 TRUE = 170
0-6 TRUE = 189
0-7 TRUE = 207
0-8 TRUE = 224
0-9 TRUE = 224