About RSLogix 500 BSL BSR

Hello friends,

When I trigger once for an application, I want to shift the 15th bit in the word address by 10 bit , so;

1000 0000 0000 0000 -> First state
0000 0000 0000 0001 -> Second state

I should be able to change that shift value as well. shift like 5,10 or 15..

Has anyone tried it before? I look forward to your help in this matter.

@asefakaratas:
I guess your array is only 16 bits long, and position 15 is the last one.
This is from manual : https://literature.rockwellautomation.com/idc/groups/literature/documents/rm/1747-rm001_-en-p.pdf

go to page 140:
For wraparound operation, set the position of the bit address to the last bit of
the array or to the UL bit, whichever applies.

And that´s what you did a wraparound. See your example.

Read the manual carefully.

Summary: the BSR is designed to shift its addressed bits by one bit position per execution, and that only on a rising edge of its input rung.

Possible solutions (there are others):

1. Fifteen BSR instructions in fifteen consecutive rungs
   1. each fed by the same rung logic to detect the rising edge;
   2. each with its own unique control structure (e.g. R6:0 through R6:15);
      1. I am fairly certain that, in RSLogix 500, control structure references cannot use indirect addressing;
   3. To shift by N bit (N in the range [:15]) positions, enable the only the first (or last) N of those instructions;
      1. Logic that increments N may be on branches with each of the BSRs, or on separate rungs before each BSR
      2. N.B. changing N on successive scans, while the input rung logic that supply the rising edge are true, can produce unexpected results
2. One BSR instruction in a loop
   1. Control the rising edge separately i.e.
      1. detect the rising edge before the loop,
      2. save the result in a bit
      3. make loop execution dependent on that rising edge result bit
   2. Unlatch the .EN member of the control structure to 0 in the loop before the BSR
   3. Put no logic on the rung of the BSR
3. Divide word by 2**N
   1. e.g
      1. N7:0 - input word with bits to be shifted
      2. N7:1 - result word with shifted bits; also some intermediate values
      3. N7:2 - N, i.e. number of bit positions to shift, 0 to 15
      4. N7:3 - divisor i.e. mask with 1 in lowest bit to be shifted and all other bits 0
      5. N7:4 - shifted sign bit position
   2. Create the following single rung:
      1. BST CLR N7:3 NXB OTE N7:3/[N7:2] NXB SUB N7:3 1 N7:1 NXB NOT N7:1 N7:1 NXB OTU N7:1/15 NXB AND N7:0 N7:1 N7:1 NXB DIV N7:1 N7:3 N7:1 NXB SUB 15 N7:2 N7:4 NXB XIC N7:0/15 OTE N7:1/[N7:4] BND
         
      2. Update to fix previous item; tested and working now
         

TL;DR

See the BSR Flow Chart (True) at the end of the BSR documentation at this link; that is RSLogix 5000, but it explains how the BSR works. the key steps to notice are

• The <examine .EN bit> conditional diamond in the upper left
• where the logic goes if that conditional of .EN finds a 1
• where the logic goes if that conditional of .EN finds a 0
• The [.EN bit is set to true ...] box under that conditional

The OP says "shift the 15th bit in the word address by 10 bit," but the example diagram shows a shift by 15 bit. So I assume the example diagram should be something likeAnyway, the issue OP is coming up against is that the BSR is designed to shift the bits in a word by exactly one bit position. and that only on a rising edge of the input rung state, so by design a single BSR executed once per scan in a program can only shift bits by one position on every other scan, i.e. on alternating scans.

So if we put multiple BSR instructions with the same control object (e.g. R6:0) one after the other, the second and later BSRs will detect a rising edge, because the first instruction sees the rising edge and changes the state of the control object (e.g. R6:0.EN)

@drbitboy:
I like all your explanations.