Siemens equivalent for simple 128-bit shift register in RSLogix

DR: once you get used to it it's great, ...


Yeah, I hear you, and I do not intend to give up. Remember I coded sine, cosine and natural logarithm in MicroLogix 1100 ladder; it's just disappointing when a decent algorithm takes longer than it should because of anemic infrastructure.


As far as ST/SCL, that is of little interest to me; sure it's Turing complete, but it seems pointless to pay to be hobbled like that*; if I was going that route I would prefer C or Python on an SBC of some sort e.g. arduino or rPI.


* and yet I enjoy ladder for pete's sake; now that's how I like my irony ;)
 
Does the S7-1200 have a STL?
L D[AR2,P#0.0]'s technique is the best unless S7-1200 has a STL that has the right instructions.
Micro controller have a rotate left through carry.
This allows shift 128 in just 4 instructions as long as there is a shift left into carry and a rotate left through carry.
PLCs tend to hide the carry, zero and sign bits.
 
I sort of agree with you, you here a lot about ST etc. on here but I also like ladder or FBD I find I can write it just as fast as ST, but that's probably because I know it better, I was just saying that I started using Siemens in the early 80's and because I spent a lot of time on many very large projects it became second nature, in it's time it was probably the most powerful system and close to what most platforms are using now i.e. the IEC (probably find they were involved in it's development as there are so many similarities). incidentally, in Siemens S5 FB's could only be done in STL so that's why I got to like it.
 
Instead of rotating all the bits, you can keep the bits stationary and instead move two pointers to the load and unload indexes. That is the most efficient way.
Downside is that if you look at the FIFO online, it is not as easy to interpret the data moving, as compared to actually literally seeing the data moving.


I used to program the FIFO buffers in the efficient way (in AB SLC500/PLC5 ladder no less) and thought myself very clever. Nowadays I program FIFOs in the ineffecient but easy to interpret way. Ease of maintenance and troubleshooting is more important.

PLCs are much more performant these days, and the compiler will do a lot of optimisation without you having to think about.



The library block thing is also a way. But then you have to study and understand the library block.

It takes a few minutes to crank out the SCL code.
And the SCL compiler in TIA will do the optimization for you and convert the code to moving large blocks of data when needed.


And in TIA you can mix LAD and SCL code in the same block, which I find brilliant.
 
Instead of rotating all the bits, you can keep the bits stationary and instead move two pointers to the load and unload indexes.


Oh of course. Thanks @JesperMP!


I've implemented that before, but I've gotten so used to the simplicity and convenience of FFL/FFU/BSL/BSR that now I whine if I can't use them!


d'Oh!
 
PeterN: PLCs tend to hide the carry, zero and sign bits.


C: all the power of the assembler, with all the convenience of assembler. ;)


Ladder/SCL/ST: all the convenience of assembler, with none of the power of assembler ;);).


P.S. thanks again to @JesperMP: I finished the TIA ladder-based shift register program on another thread, using Function Block instances for each of six line-valve-diverter stations, pretty quickly 'n'all.


Maybe I was the problem, not Siemens.
 
This works and is simple. I created a bit array and then use MOVE_BLK within the array, the second Move_BLK takes care of the overflow bit.

Bit shift.JPG
 
And a static array, with indices that keep track of the head and tail of the FIFO, emulating a dynamic shifting FIFO is the most efficient, especially when dealing with more bits than the longest integer has (64 for S7-1500; 32 for S7-1200).



I wonder where BrianG's MOVE_BLK method comes in w.r.t. efficiency.
 

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