Detailed scan question for Rockwell Logix PLC

steve9199

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I have a question about differences in logic solving output instructions when they are placed in series as opposed to parallel. Getting down to the machine language level, what is the real difference in solving:


----------------(COP)---(MOV)----(CPS)-----(OTE)


vs


----------------(COP)
|
|------(MOV)
|
|------(CPS)

|
|------(OTE)

(for example)

These outputs could be OTE, COP, MOV, whatever. What are the true differences (down to the machine level, maybe timing micro or nano seconds???, maybe something else) difference when the outputs are in series verses in parallel?

I am asking because a colleague in China was told by their Rockwell rep that the solving is significantly different

Thanks in advance
 
I--()--()--()--I
VS. I-----()--I
. I--()--I
. I--()--I

Compiles as "OTE OTE OTE" vs "BST OTE NXB OTE NXB OTE BND". It's four more instructions. As fast as a ControlLogix runs it's generally inconsequential. Maintenance electricians are sometimes confused by linear coils, so I avoid them in routines maintenance might need to troubleshoot. Data manipulation instructions (MOV, CPS, etc.) I often place in series if I have to do them in ladder as opposed to ST where they belong.
 
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From my understanding, in your second example, it will scan upward? So the OTE activates first, then CPS, then MOV, and finally COP. Whenever I am using Concat instruction to combine strings, I always place the first letters on the bottom of the rung and the last letters of the string on the top of the rung. As far as nanosecond differences, I am unsure, but I'm sure the PLC of choice plays a part. But someone else can verify what I said for this example, I am unsure.

For your first example, I just looked at an old program, and it scans the left most output first. I am using Concat again, so the first letters are always the left-most instructions on RS Logix V20. Unsure of speed differences b/w example 1 and 2.
 
What are the true differences (down to the machine level, maybe timing micro or nano seconds???, maybe something else) difference when the outputs are in series verses in parallel?

Welcome to the Forum!

The scantime will be shortened by several microseconds for each removed branch or rung; the exact value depends of the magnitude of the change and the type of the participating Output instructions.

I am asking because a colleague in China was told by their Rockwell rep that the solving is significantly different

I dunno about that...:D...One of the two parties is employing some sort of "alternative facts".

Any Logix application rung Output instruction state is determined by solving the logic result of the states of the preceding Input instructions only.

There is no difference between the Logix CPUs' approach in solving the logic result of a rung or a rung branch.

It used to freak out 'old timers' or Maintenance personnel back in the time, however, I think they got the hang of it by now.

Let's say you have to Unlatch hundreds of BOOL instructions upon a First Scan Pass or continuously CPS several full networks worth of VFDs data at all times; it makes it so much easier to visualize/comprehend the logic immediately instead of wearing your mouse's scroll wheel through hundreds of rungs or rungs' branches.
 
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Maintenance electricians are sometimes confused by linear coils, so I avoid them in routines maintenance might need to troubleshoot.

I am pretty sure any Maintenance electrician will be infinitely grateful if the .DN/.TT flags of the TON/TOF instructions are immediately trailing them instead of being pitched all over the application requiring extensive searches for logic comprehension.
 
I have a question about differences in logic solving output instructions when they are placed in series as opposed to parallel. Getting down to the machine language level, what is the real difference in solving:


----------------(COP)---(MOV)----(CPS)-----(OTE)


vs


----------------(COP)
|
|------(MOV)
|
|------(CPS)

|
|------(OTE)

(for example)

These outputs could be OTE, COP, MOV, whatever. What are the true differences (down to the machine level, maybe timing micro or nano seconds???, maybe something else) difference when the outputs are in series verses in parallel?

I am asking because a colleague in China was told by their Rockwell rep that the solving is significantly different

Thanks in advance

From the first timing manual I found (1756-RM087E-EN-E - May 2005) there is no listing for BST, NXB, or BND - Branch start, Next Branch, or Branch End

So it is not much time. NOP or No Operation, is 0.05 microseconds to execute.

I would not value the opinion of that 'Rockwell rep' with regard to programming ...
 
I am pretty sure any Maintenance electrician will be infinitely grateful if the .DN/.TT flags of the TON/TOF instructions are immediately trailing them instead of being pitched all over the application requiring extensive searches for logic comprehension.


I have absolutely no idea what you are talking about...


The .DN .TT and .EN members of the timer tag can be addressed anywhere in the code, in exactly the same way you can look at a Counter's accumulator value 5000 rungs away. Every tag can be referenced anywhere you want (within the scope).
 
I have absolutely no idea what you are talking about...


The .DN .TT and .EN members of the timer tag can be addressed anywhere in the code, in exactly the same way you can look at a Counter's accumulator value 5000 rungs away. Every tag can be referenced anywhere you want (within the scope).


I think what he was referring to the fact that some of us Bubbas (Bubbi?) Get confused if all the associated bits for a timer, counter, etc are not within one rung of timer, counter, ect, itself. If I were a more educated man, I might think he was in fact having a bit of fun at our expense. Fortunately for me, my thoughts seldom get past; coffee, chair, break time.

But to get back to the OP's question, in a modern Logix processor, say L7x and newer, is there really going to be a noticeable difference in scan time if there are 500 BST and 500 BND instructions in a program? I realize that the overall size of the program comes into play, but I'm thinking of situation where the controller is selected to match the task from the start.

Bubba.
 
I might think he was in fact having a bit of fun at our expense

No pun was intended...:D...

Yes, one could insert Timer and Counter flags anywhere within an application, within the same rung as the instruction itself (Logix platform only) or thousands of rungs away.

However, since I'd say that more than 75/% of the TON/TOF instructions are 'single' use (one flag dedicated to only one delayed condition) the placement of the flag immediately after the instruction greatly improves the efficiency of troubleshooting especially when the software runs in Online mode.

When one is able to visualize the entire delayed command logic in one animated rung (as opposed to searching between the instructions and flags), finding the malfunction's culprit is a breeze.
 
..... I just remember reading about reverse scanning the outputs at the rung, so unsure of this particular example.

This "reverse scanning" is most likely referring to a technique that was introduced many years ago, on the SLC (and possibly the PLC5 and 5/250) platform(s).

The intention was to speed up execution of the logic, by skipping the rest of the rung once it has gone false. The processor would jump to the end of the rung, and work backwards, turning off non-retentive outputs, until it found the last conditional instruction. The greatest benefits would ensue if instructions most likely to be false were placed at the left-hand end of the rung. The technique was perfectly valid in the aforementioned platforms, because of the rigid rules imposed for output instruction placement.

However, along came Logix5000, which threw away all those instruction placement rules, and allow programmers to program output-type instructions anywhere on a rung, there is simply one rule, you must have an output-type instruction as the last instruction on the rung. You can begin the rung with an "output" instruction(e.g. a Timer), follow it with a conditional instruction, then an OTE, then another XIC, XIO or ONS, followed by an OTE, OTL, OTU, or a MOV etc.

But now, Of course, this "reverse scanning" technique is not valid for Logix5000 code, and it cannot work that way. But that optimisation strategy is still taught in Rockwell Training courses, for a totally different reason. In Loigix5000, once a rung (or branch) has been turned false by a conditional instruction, the processor no longer has to "fetch" the states of following conditionals from the databases, because you cannot make a rung (or branch) true again. All instructions are "scanned", but there will be no need to interrogate the databases. This is how Logix5000 execution speed is improved by placing instructions most likely to be false at the head of the rung.
 

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