PLC rung scan implications

This is a good one to think on, can someone take it a step farther.

If the add instruction is executed each scan, then does it:

Evaluate and then overwrite the N7:0 in question with the same value each scan or is there a simple bit function under the hood that says don't change the value.

A simple bit level output will go and write a 1 or a 0 into its data table or tag value depending on the rung condition each scan no matter if your using a PLC5, SLC or CLX would it not.

Are the rules the same for Instructions at the Word level and larger. Do they overwrite themselves each scan??

Interesting Stuff, if you can expand on this, that would be great.

Thanks,
BCS
 
Just to expand on what I was saying in the last post:

For instance with a timer it has and ENABLE BIT, if the rung preceding the timer is True then it will go and write a 1 into the ENABLE BIT BOX and if the rung preceding it is False then it will go and write a 0 into the Enable Bit Box and it will do this each and every scan.
You can go and physically see this in the data table or tag values and you can set up a branch with a XIO (TON.EN) and an ADD instruction to prove this.

But concerning an ADD instruction there is no ENABLE BIT BOX that you can go and see.

So what is really happening in this case. (Makes you think)

BCS
 
Hello again guys,
Not trying to keep bothering you with additional post to this one but I am sitting here bored and curious about this one.
Kind of surprised that no one has come back with an explanation on this yet.

I am not trying to be wishy washy but the more I think on this one the more my mind wants to say that the ADD (or any Math instruction for that matter) does not execute if the rung instructions preceding it are false.

Not saying this is correct or not, just saying it would seem this way since we cannot show otherwise.

I am going to lay out a few points, please let me know what you think on each and if I am off base.

1) The Ladder that ASF shows in his post with the unconditional ADD instruction on the Parallel Rung..... This ADD instruction will work the same no matter if it is installed in a PLC, SCL, MLX or CLX, if the first instruction on the main rung is true then the ADD will continue to incriment unconditonally every scan.
But if the first instruction is false then it will not increment, does not matter what A.B. Platform we are using. (would every one agree with this???)

2) So if that is the case then if the first XIC instruction is false.....How is the ADD instruction Executing anything.
There is nothing in the data table/ tag values that would suggest this instruction is going out and writing anything. (Unless of course it is actually going out and over writing the same value in the destination word, dint, real, etc.)
If this is the case then the same would be said for MOV, COP, etc instructions that are preceded by false conditions on the rung.
(Since no one came back right away and confirmed or denied this it got me wondering)

3) I started looking through a training manual and found a small example of a output that does nothing if instructions are false prececing it on the rung.
That example is the latch and unlatch instructions.
They are at the bit level so this comparison is apples to apples.

A normal OTE bit output preceded by false instructions will go and write a 0 in its BIT BOX in the data table or tag value.

However if we are talking about a Latch or UnLatch instruction.....when they are preceded by false instructions then they do nothing for that scan, they do not go and write a 1 or a 0 in the bit box. it simply stays the state that it is in. (Does everyone agree with this also.)

4) So with this example does everyone still say that Math, MOV, COP, etc instructions are EXECUTED every scan???
And if so how are they EXECUTED???
(How can we show with out a doubt that something happens in the data/tag tables each scan for these type of instructions.)

I am not saying correct or incorrect, or trying to be a smarta$$, only bringing up points and questions because I am curious about this now that we are on the subject.

If anyone has any thoughts or experience on the subject, I would be very interested in learning more about this. I am sure others would like to know also.

Thanks,
BCS
 
Last edited:
Hello again guys,
I am not trying to be wishy washy but the more I think on this one the more my mind wants to say that the ADD (or any Math instruction for that matter) does not execute if the rung instructions preceding it are false.

It will still execute, but "execute", but not in the sense of "add a + b and store in destination". It will "execute" in that if it's rung in condition is false, it's rung out condition will become false, and vice versa. You can prove this by setting up my test rung, adding in the xic before the add, and then turning the first bit on the rung on. You will notice that the add instruction does not add, and the OTE stays off. Then turn on the XIC just in front of the ADD. The ADD will add the two values, and your OTE will turn on.

Now. Turn your xic before the ADD back off. What happens to the OTE? It turns off. Why? Because the rung out condition from the ADD instruction is now false, along with the rung out condition from the two other XIC branches, and so the rung in condition of the OTE is now false.

If the ADD instruction did not execute at all if the preceding XIC were false, then it's rung out condition would remain on. As this is not the case, we know that the PLC encounters the add instruction, ignores the values and destination, but still does SOMETHING (i.e. turns off the rung out condition).

Bering C Sparky said:
1) The Ladder that ASF shows in his post with the unconditional ADD instruction on the Parallel Rung..... This ADD instruction will work the same no matter if it is installed in a PLC, SCL, MLX or CLX, if the first instruction on the main rung is true then the ADD will continue to incriment unconditonally every scan.
But if the first instruction is false then it will not increment, does not matter what A.B. Platform we are using. (would every one agree with this???)

You will not be permitted to use the add instruction in this way on a micrologix or SLC. Only CLX platforms support this type of nesting.

Bering C Sparky said:
2) So if that is the case then if the first XIC instruction is false.....How is the ADD instruction Executing anything.
There is nothing in the data table/ tag values that would suggest this instruction is going out and writing anything. (Unless of course it is actually going out and over writing the same value in the destination word, dint, real, etc.)


If this is the case then the same would be said for MOV, COP, etc instructions that are preceded by false conditions on the rung.
(Since no one came back right away and confirmed or denied this it got me wondering)

You cannot monitor the rung in and rung out status for these instructions (well, not to my knowledge), and you're right that it's not writing data to anything that you can see - but the PLC still evaluates the instruction

Bering C Sparky said:
3) I started looking through a training manual and found a small example of a output that does nothing if instructions are false prececing it on the rung.
That example is the latch and unlatch instructions.
They are at the bit level so this comparison is apples to apples.

A normal OTE bit output preceded by false instructions will go and write a 0 in its BIT BOX in the data table or tag value.

However if we are talking about a Latch or UnLatch instruction.....when they are preceded by false instructions then they do nothing for that scan, they do not go and write a 1 or a 0 in the bit box. it simply stays the state that it is in. (Does everyone agree with this also.)

Again, it will still evaluate it and change the rung out condition to suit. In CLX you can put multiple OTL or OTU in series - if your OTL has another OTL after it, that next OTL needs to know the rung out condition of the previous one to know if it's supposed to latch it's tag or not.


Bering C Sparky said:
4) So with this example does everyone still say that Math, MOV, COP, etc instructions are EXECUTED every scan???
And if so how are they EXECUTED???
(How can we show with out a doubt that something happens in the data/tag tables each scan for these type of instructions.)

It says exactly that in the technote: every instruction on the rung is executed. They perform functions that you can see when their rung in condition is true, and functions that you (usually) can't when their rung in condition is false.

I'll raise the example again of a rung I programmed that caused PLC faults due to faulty indirect addressing. I AFI'd the whole rung until I could track down the problem, but it still kept faulting on that rung. So that says to me, that even though every instruction on that rung had a false rung in condition, even though it doesn't perform any actions on it, the PLC still evaluates each and every instruction - even to the extent of checking the validity of tags and pointers within the operands that it's not going to do anything to.


Aaaaaanyway it's friday here and it's 5 past beer time so I'm off for the weekend! Hope I've managed to explain that somewhat coherently! 🍺
 
Nice,
Enjoy your beer,

Thanks for giving me something to think over.

It will still be a month or so before I return to work where I can play with this on a bench with software and hardware. But I look forward to experimenting with it when I get back.

Still interested in knowing WHAT function it is that these instructions perform when preceded by false instructions though.

Have a good one.
BCS
 
Hello again guys,


1) The Ladder that ASF shows in his post with the unconditional ADD instruction on the Parallel Rung..... This ADD instruction will work the same no matter if it is installed in a PLC, SCL, MLX or CLX, if the first instruction on the main rung is true then the ADD will continue to incriment unconditonally every scan.

Incorrect. The PLC-5, SLC-500, and MicroLogix (SLC Based ones) do not allow output instructions within a rung. All outputs must be in the rightmost column. Only the Logix based platforms allow for inline ADD (or other output instructions), so they have to process all code.
 
As a final test I wrote the accompanying RSLogix 500 project (had to use a 5/05 for the RHC command) (My ears were burning from the OP)

I wrote 100 lines of checking the most-common-on (output on) then branching down to check the start PB. Then I wrote 100 lines checking the start PB & branching down to check the output. After each 100 I record the time & the last line compares the scan times.

With all the outputs OFF the scan times were identical, but when I turned all the outputs ON & tested with the Start PB back off, there was a noticeable difference - 3ms speed increase for doing it my way - see picture.

Going to rewrite it (later) to test the same start portion, but swap the Stop PB & MCR On between the 100's.

Capture.JPG
 

Attachments

  • Scan Time Test.zip
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Re-wrote the test.

With the start PB on & the Stop PB off there was a very increased scan time difference (19 vs 35ms) checking the stop PB first & last - see the attached picture.

So it is true, checking the most-common-on then branching down towards the least-common-on is faster and checking the most-common-off item first results in faster scan times, as the checks after that are neither checked (what I was told - the scan jumps to the output once it encounters a false instruction) or if the remaining instructions are checked in a forced false state after the initial false instruction is processed.

1Capture.JPG
 

Attachments

  • SCAN TIME TEST2.zip
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I have often seen statements that arranging rungs so that the condition most likely to make the whole rung TRUE (or FALSE) should be placed to be evaluated first to speed up scan time.

This implies that, upon determining that the rest of the rung conditions are irrelevant to deciding the ultimate TRUE or FALSE state of the rung, the system will bypass (or in some way shorten the evaluation of) further conditions and jump right to output processing.

While this sounds efficient does anyone have a reference to an official technical publication which specifically states this behavior in the evaluation of rungs? (I'm thinking primarily Allen Bradley or AutomationDirect PLCs since those are the ones I'm most familiar with.) I'm looking not just for a recommendation of rung structure but an actual statement as to how this 'evaluation shortening' takes place.

I don't have a reference handy, but I do remember, way back in the old days, that AB published an instruction timing chart. This chart would tell you the approximate time of execution of a given instruction. There were different times listed. Execution Time if TRUE, Execution Time if FALSE, and TRUE always took longer.

I don't know what to imply about that, especially with regard to branches and such, but, I do remember as a bored technician on night shift one day, creating a program with thousands of rungs, all the same (CopyPaste), and then writing a scan timer routine, to see if, in fact, this was true. I think I even used an instruction with the largest time difference as the test...SIN COS XOR or something like that.

It was.

Now, this was likely a PLC-2 with ICOM, or a PLC-5.

So, the evidence is Observational, and, like many things inside these boxes, we, as end users, will likely never get any detailed response, except to say that 'that's how it is'.
 
I too was looking at those sort of timings, in this case it was a Micrologix 1100 manual. As a side note I saw that some of the ASCII output instructions had a LONGER execution time in the 'If FALSE' column.

An earlier reply to this thread referenced a manual which had a statement that many of the 'unnecessary instructions' (because the state of the rung had already been decided) took 'zero time'. Even though it was in the manual I somehow doubt that statement given the true/false timing table listings.

As you note we'll probably not get a detailed answer, just general recommendations. A detailed answer would require discussion of actual system code which handles the scanning.
 
... the 'unnecessary instructions' (because the state of the rung had already been decided) took 'zero time'. ...

That's what I was told years ago & I base my programming on - after a false instruction is encountered on a line, it immediately jumps to the output & turns it off, bypassing any later instructions on the line. And my scan time test #2 above does seem to verify that, with a large reduction in scan time when the first instruction is false vs the last instruction false - scan time was almost cut in half not processing the later instructions.


Edit: one more post & I hit 300, who buys the cake?
 
Not being pedantic

That's what I was told years ago & I base my programming on - after a false instruction is encountered on a line, it immediately jumps to the output & turns it off, ...
Just adding a clarification for those new to or unfamiliar with ladder logic. An OTE output will be turned off - because the rung condition passed to it is false. Other instructions like CTU, and file instructions will have their EN bit reset so to be in readiness for the next false-to-true transition. OTL and OTU will simply maintain their current state.
 

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