2 out of n voting block in RSlogix 5k

Dear Experts
Is there any block for 2 out of n voting block in RSlogix 5k
or any short cut method to create this

Best Regards
Muhammad Asim Khan

asim_rana said:

Dear Experts
Is there any block for 2 out of n voting block in RSlogix 5k
or any short cut method to create this

Best Regards
Muhammad Asim Khan

Click to expand...

What exactly do you want to do?

Are you looking to move part of a word. Like 2 letters out of 8 for lack of a better example. If that is the case you can use a MVM masked move that will allow you to pick what letter's you would like to move.

That's seems like what your asking but not sure more detail would be appriciated.

There are no voting blocks pre-defined, so you'll have to roll your own. In FBD, you could take a shortcut by using the SSUM blocks, assigning 1.0 to all inputs, and using 8 digital inputs to enable each channel. 0 inputs on, output would be 0. 1 input on, output would be 1, 2 inputs on, output would be 2, etc.

The way I do this logic in ladder is to move zero into an integer, in the branch below that increment the integer depending on a leading bits state, and repeat the branch for the number of inputs you are counting. Every scan of the logic the integer will update to the number of inputs on or off.

Just curious, what is a "voting block"? Is it like a select function or counting true bits in a byte/word?

I would guess that he is working on a safety interlock system (SIS). In these systems, many times you will use 3 or more devices sensing the same thing, when any 2 of them detect a problem, action is taken. The number of devices depends on the degree of reliability required.

I'm familiar with all the options available in the Controllogix platform, but in a DCS, I would use a "Calc" function block.

IN BI01
IN BI02
etc
IN BI16

ADD 16

Then if the sum is greater than 1 take action.

This is similar to a recent query over at MrPLC to which I offered the attached solution using FBC. In that case they were looking for 3 or more inputs from a group of 9.

As clear as mud... Gerry... How about a simple conceptual explanation.

OkiePC said:

Just curious, what is a "voting block"? Is it like a select function or counting true bits in a byte/word?

Click to expand...

A voting block, in general terms and those which I'm understanding the OP to ask about, is a circuit that becomes true whenever 'n of x' inputs is true.

So, a 2 of 16 voting function would output true if any two inputs are on, and false in all other cases. A 4+ of 16 would output true any time 4 or more inputs are on, false otherwise.

Not to be confused with voting receiver technology, where a discriminator determines which remote-receiver is getting the strongest signal from a particular transmitter, and selects that as the primary receiver. This is used in communications repeaters mostly.

Oh, and original poster... if worst comes to worse, the minimalist NAND solution to any logic problem can always be solved with a Karnaugh Map.

rdrast...

If you have been around (at PLC.net) long enough... then you know that I am "the" major proponenent for Karnaugh Maps. However, in this case, although I haven't found it yet, I believe there is a way to make the determination much faster than a K-Map could.

At the very least, one could exercise a special-function program, or a sub-routine with jumps, to divide by 2 until the result consists of a quotient greater than "0" and a remainder of "1". If that occurs then, without a doubt, more than one input is ON!

However, I'm still working on trying to make this determination in a single rung.

This is an interesting problem.

I'm still waiting for Gerry to describe his method in a conceptual manner.

Terry Woods said:

As clear as mud... Gerry... How about a simple conceptual explanation.

Click to expand...

"When enabled, the FBC instruction compares the bits in the Source array with the bits in the Reference array and records the bit number of each mismatch in the Result array.
The FBC instruction operates on contiguous memory."

In my example, the two resets and the unlatch cause the FBC instruction to initialise and execute on every scan.
The source array contains the input information.
The reference array contains the desired state of the inputs - in this case it was all 1's but could be any pattern of 1's and 0's.
The Compare Control and Result Control are essentially counters but instead of .PRE and .ACC attributes they have .LEN and .POS attributes (length & position). The value of the Result Control's .POS attribute tells us how many mismatches were found. When set, the .FD attribute (found) indicates that at least one mismatch exists. Examining the result array will reveal which bits are a mismatch.

Hmm... I am not sure if this is what the inquiry was about but I am using "tree-out-of-five" method for inline inspection stations... that is, set an alarm if any three of the last five product inspections failed.

See the example attached. MB13520 through MB13524 are the first five consecutive bits of a shift register word, containing pass/fail information (i.e. a bit is on if the part in that shift position failed the inspection).

LadderLogic said:

Hmm... I am not sure if this is what the inquiry was about but I am using "tree-out-of-five" method for inline inspection stations... that is, set an alarm if any three of the last five product inspections failed.

See the example attached. MB13520 through MB13524 are the first five consecutive bits of a shift register word, containing pass/fail information (i.e. a bit is on if the part in that shift position failed the inspection).

Click to expand...

It looks like it will detect MB13520 plus any other 2 of 4

The bi#ch of the problem is that, as posed, he is looking for 2 out of N.

N could be a very large number!

So, the real quest is... how to determine 2 out of N (a potentially very large number) in a single scan?

If this were a nuclear melt-down, or a space-craft landing on the moon, you would want to know the answer really quick, wouldn't you? Especially in terms of critical decisions that are based on the milli-second.

It could be done very easily with a special-function or sub-routine with jumps... however, as far as I'm concerned (and, I would expect, with any of the other purists that might be around), the challenge is to make the determination in ladder-code, or function-block-code, or STL-type-code, in a single scan, with a minimum number of rungs or function-blocks. That is... make the determination, as fast as possible, without affecting scan-time... at least, without affecting scan-time too much.

It occurs to me, although I might be wrong - believe it or not, that this should be determinable with AND-OR-NOT-NOR-XOR logic in only a rung or two (maybe three... or four). I'm still working on it.

Again, this is an interesting problem.