Reverse parallel logic?

+1 for Daba's method, I always generate my own dummy and shorting flags (usually Steve_flag1, 2, etc). It is easier to cross ref to find.
If I remember correctly you can disable the shorted branch and AFI error trapping when you compile in the options.


Steve

When I'm walking away from a program that I've finished making changes on, I never leave AFIs or shorted branches. That's when I put the kit bit (what we call them) in place, usually and XIC XIO OTL rung at the top of the main subroutine, and then an XIC in place on any rung that was changed.

I just like using the AFI and shorted branches when I'm still working on the logic, as it doesn't cause any issues (just warnings, not errors) and if I've forgotten anything, I'm reminded as soon as I attempt to compile the logic changes.

We created a UDT with Bools and Reals and DINTS etc called user.

Then each Engineer has that UDT as their name.

That way we have everything we need in a simple UDT that we can use to temporarily add to code for fault finding etc.

Then we know exactly who has put it in.

Cheers

Mark

janner_10 said:

I remember you telling us about this in one of your classes in MK, still do it to this day as I thought it was such a good, simple idea.

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It's good to know someone was listening, thanks janner_10 !