Sequential Logic to AB PLC

Tze

Member
Join Date
Jan 2003
Posts
2
I have problems understanding the bit flip-flopping of various Reset-Set Function blocks. Here are some examples (All have a Set input and a Reset input)

1) Reset Dominant with only Reset Output
2) Reset Dominant with only Set Output
3) Reset Dominant with a Set Output and Reset Output
4) No set/reset overrides with a Set Output and Reset Output
5) No set/reset overrides with a Set Output

I personally think 1) and 5) have similar functionality if reversing the input bits.

Please advise where I can obtain the truth tables of the reset-set logic blocks. Also, are there any PLC programming examples for Reset/Set logics?

Thank you in advance for your help! Happy New Year!
 
It sounds like you are really talking about the "Gate-type" Flip-Flop. I'll get back to that.

When referring to SET & RESET in a PLC, you are referring to nothing more or less than an explicit, do-it-right-now, Turn-it-ON or Turn-it-OFF instruction.

If applied to a control relay (memory-bit), the effect happens IMMEDIATELY! This bit can then be referenced immediately afterward (in the next rung, and in some PLC's, "later" within the same rung!).

If applied to an Output, the "right-now" effect doesn't happen unless you use "SET IMMEDIATELY" or "IMMEDIATE SET". Otherwise, the effect occurs when the Output Image Table is updated.

Tom Jenkins will be happy to express all of the cautions you should keep in mind when using SET/RESET.

SET/RESET certainly can be problematical if you don't keep tabs on what you are doing. You can very easily turn on the water in the tub. But you had damned well better keep in mind the fact that the tub is running! SET/RESET can be used in a million different ways (well, a bunch, anyways!).



Now, as far as the "Gate-type" Flip-Flop, there are two types; the NOR-type and the NAND-type.

The TRUTH-TABLE for the NOR-type goes like this...
     S R  Q  Q'
1 0 1 0
0 0 1 0 (after S=1, R=0)
0 1 0 1
0 0 0 1 (after S=0, R=1)
1 1 0 0 <-- NOT VALID


.


The TRUTH-TABLE for the NAND-type goes like this...
     S R  Q  Q'
1 0 0 1
1 1 0 1 (after S=1, R=0)
0 1 1 0
1 1 1 0 (after S=0, R=1)
0 0 1 1 <-- NOT VALID

 
Since you mentioned A-B, I'll assume you're talking about FBD in ControlLogix. And from your description, I'll guess that you're looking at a diagram that someone else has programmed.

When making the diagram, you have the option to display or hide the various inputs and outputs of each individual block as required to reduce 'clutter'. (Accessed via the ellipsis button in the top right corner of the block).

There are 4 types of flip-flop available: D, JK, Reset-dominant, Set-dominant.
The 'dominant' types specify the state of the outputs when both the set and reset inputs are true at the same time. The D type transfers the state of the D input to the Q output on a true transition of the clock input. The JK type toggles its outputs for each true transition of the clock input (not quite the same as the JK flipflop I learned about in school). For both the D and JK types, the Clear input is dominant.

1) Reset Dominant with only Reset Output
2) Reset Dominant with only Set Output
3) Reset Dominant with a Set Output and Reset Output
I would guess these are all the same block with different combinations of outputs displayed.

4) No set/reset overrides with a Set Output and Reset Output
5) No set/reset overrides with a Set Output
And I would guess that these are possibly JK type, again with different display options.
 
"Tom Jenkins will be happy to express all of the cautions you should keep in mind when using SET/RESET."

Well pardner, their ain't enough time t' express them ALL .

I discourage the use of set and reset primarily because of the difficulty this structure can cause in de-bugging. It is hard to keep track of what the logic is doing while you are monitoring program operation on-line. For example, it is possible for all of the bits on a rung to be showing "ON" but the coil or output be "OFF" because logic later in the program has reset the coil. At 10:00 PM with your rump on a bucket and a contractor screaming in your ear this situtation is not conducive to rapid problem resolution.

A good old latching contact, on the other hand, makes it obvious what is going on. If you have mulitple event combinations that should trip the same coil or output you simply use separate status or flag coils for each combination and have them turn on and latch the event in question.

With many platforms it is possible to have the same coil set and/or reset many times in the same program. As Terry points out it is difficult to keep track of the final status of the coil, and which is the overriding event that caused it to have that status.

Now, in moments of weakness, I have used logic with set and reset, but only one of each per program, and I comment the devil out of them. Like anything else this logic is OK if you do it properly, but set and resett low on my list of command desirability.
 
Last edited:
Truth table

Thanks for your replies. Attached please find the truth tables that I just created. I need to convert FBD into ladder logic and I need verification on them, especially cases 3 & 4.

Again, I am not familiar with these kinds of logics and please advise where I can obtain more information in regards to this matter.
 
Your truth table for case 1 should list the Q' (reset) output - states as in case 3.

As for cases 4&5, you will need to take "context" into consideration - i.e. how are they used and what is meant to happen.

I take it you're NOT looking at FBD on CLX
 
Must not be Siemens Step 7 because it will auto convert from FBD to ladder but then again it uses blocks in both, the Set Reset is a single block (or box if you prefer that description better).
FBD
fbd.jpg

LADDER
lad.jpg
 
Tze,

It sounds to me like you might be over-complicating this with too much “relative-terminology”. It really is a very easy concept to understand. Maybe this will give you a better picture.

HARDWARE VERSION OF R-S
A complete “Hardware” version of an R-S device consists of 4 elements:

“S” = SET-Input
“R” = RESET-Input
“Q” = OUTPUT
“Q’” = “NOT-Q” Output

In Hardware, it is sometimes necessary to “positively-assert” the absence of an output signal. That is, if “Q” is Not ON, then, turn on a signal to “positively assert” that “Q” is OFF. This is accomplished by simply applying the “Q-Output” signal to an Inverter. The Output of this Inverter is called “NOT-Q”. Both outputs, “Q” & “NOT-Q”, physically exist and are available for use.

“NOT-Q” will always be the opposite of “Q”.
If “Q” = 1, then “NOT-Q” = 0.
If “Q” = 0, then “NOT-Q” = 1.


SOFTWARE VERSION OF R-S
When speaking in terms of a PLC, a complete “Software” version of an R-S device typically*** consists of only 3 elements:

“S” = SET-Input
“R” = RESET-Input
“Q” = OUTPUT

(*** I say typically because your information seems to contradict that. It appears that you can select which output you want to use, "Q" or "NOT-Q"... is this so? Seems weird.)

Typically, in a PLC, the absence of the output signal is “asserted” simply, and only, by the absence of the signal. That is, if “Q” is Not ON, then “NOT-Q” is IMPLIED. If you wish, you can very easily create a “pseudo-positive-assertion” by means of the following:


Q
--|/|-----------( NOT-Q )


.
In a PLC “R-S Logic-Block”, the state of “Q” determines whether, or not, the block provides “power-flow” to the next element in the rung. If “Q” = 0, then “power-flow” is disabled; the following element does NOT execute. If “Q” = 1, then “power-flow” is enabled; the following element DOES execute.

In some PLC’s, “Q” can be referenced. The state of “Q” can then be determined by means of the --| |-- and --|/|-- symbols. This allows for subsequent activity (in later rungs) based on the current state of “Q”.

THE DOMINANT FACTOR
The Hardware version of an R-S device does not respond predictably in the case where both the SET-Input and the RESET-Input are ON. The Truth-Table for a Hardware R-S device indicates that an input combination of S=1 and R=1 is NOT VALID.

The Software version can be forced to respond predictably. The response, in the case of S=1 and R=1, is determined by specifying a “Dominance Type”.

If the “Dominance Type” is specified as “SET DOMINANT”, then, in the case where S=1 and R=1, the Output “Q” is “SET”; that is, “Q” = 1.

If the “Dominance Type” is specified as “RESET DOMINANT”, then, in the case where S=1 and R=1, the Output “Q” is “RESET”; that is, “Q” = 0.

TRUTH TABLE
When trying to analyze the Truth-Table for either the Hardware Version –OR- the Software Version, it is easier if you simply look at the “S”, “R”, and “Q”; ignore the “NOT-Q” for now.

3e16de324a059684.gif


The Truth-Table on the Left shows the responses of a "SET DOMINANT" R-S Logic Block. The Truth-Table on the Right shows the responses of a "RESET DOMINANT" R-S Logic Block.

In Case-1, the Question Marks indicate that the states of "Q" and "NOT-Q" are what they were after the last operation.

Cases -1, -2 and -3 are identical. These cases indicate the response of the R-S device regardless of the "Dominance Type" and regardless of whether the device is a Hardware Version or a Software Version. This is because there is no logical conflict.

The effect of the "Dominance Factor" shows up in Case-4.

In the Left Truth-Table the “Dominance Type” is specified as “SET DOMINANT”.
In Case-4, where S=1 and R=1, the Output “Q” is “SET”; that is, “Q” = 1.

In the Right Truth-Table the “Dominance Type” is specified as “RESET DOMINANT”.
In Case-4, where S=1 and R=1, the Output “Q” is “RESET”; that is, “Q” = 0.

"NOT-Q"
Now, for any particular case, if you want to know the state of "NOT-Q", simply INVERT the state of "Q".

The two Truth-Tables, shown above, should be all you need to have all of the relevent information.


You said...

1) Reset Dominant with only Reset Output
2) Reset Dominant with only Set Output
3) Reset Dominant with a Set Output and Reset Output
4) No set/reset overrides with a Set Output and Reset Output
5) No set/reset overrides with a Set Output

I personally think 1) and 5) have similar functionality if reversing the input bits.


My interpretation...

It appears that you are saying that you can select which output you are going to use... seems a little weird to me.

1) Reset Dominant with only Reset Output
In this case, if S=1 and R=1, then "Q" = 0 and "NOT-Q" = 1
-AND- in this particular case, "power-flow" is determined by the state of "NOT-Q".

2) Reset Dominant with only Set Output
In this case, if S=1 and R=1, then "Q" = 0 and "NOT-Q" = 1
-AND- in this particular case, "power-flow" is determined by the state of "Q".

3) Reset Dominant with a Set Output and Reset Output
In this case, if S=1 and R=1, then Q = 0 and NOT-Q = 1
-AND- in this particular case, "power-flow" is determined by...???
This one is confusing. Are you sure that your terminology is correct?

This makes me wonder if this particular logic-block is designed to NOT provide flow to a next element.

4) No set/reset overrides with a Set Output and Reset Output
In this case, if S=0 and R=1, then...??? RESET "over-rides"???
"Over-rides" what???
Again, this one is confusing. Are you sure that your terminology is correct?

5) No set/reset overrides with a Set Output
In this case, if S=0 and R=1, then...??? Q = 1???
Again, this one is confusing. Are you sure that your terminology is correct?

I personally think 1) and 5) have similar functionality if reversing the input bits.
I can't speak to this because I don't understand Item-5. Nor can I understand this question... entirely.


Comments on your Tables...

Table-1: RESET Dominant with only RESET Output.
If Reset Output implies using the "NOT-Q" output, then, the Table Output should indicate "NOT-Q" instead of "Q". All of the output values should be inverted.

Table-2: RESET Dominant with only SET Output.
This Table appears correct.

Table-3: RESET Dominant with SET Output and RESET Output.
This Table appears correct.

Table-4: No Set/Reset Over-rides with a SET Output and RESET Output.
Seems not to make any sense. At any rate, Case-4 in this Table is wrong. "Q" and "NOT-Q" should NEVER be equal!

Table-5: No Set/Reset Over-rides with a SET Output.
Again, seems not to make any sense.

Maybe after reading this you can take another look at your source. Then, maybe, you might be able to develop a different (better?) description.

Even if you do figure it out, I hope that you come back and provide an explanation.
 

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