SLC 5/03 data loss

[andydaoust]

We have a SLC 5/03 which is suppose to balance the run hours on three different 75 hp fans. The operator selects the number of fans to run based on airflow requirements. The PLC then selects which fans to run based on hours. The programmer built an hour meter by using a RTO with a base of 1 sec and a preset of 3600. The done bit clocks a CTU, so it keeps track of hours ran. The program determines which fan(s) to run based upon the accumulated value in the CTU. Here is the problem. The PLC is not on UPS. Every month there is an emergency generator test, which drops the power to the PLC. When power is restored the accumulated value is reset to zero. This would not be a problem if the program originally kept the hours balanced. The person who programmed the logic originally used the command to run bit to start the timers instead of motor control feedback relay contact that would have verified that the motor was running. So if the motor tripped due to a MCC fault or was not in auto the PLC timers still ran. Now there is thousands of hour’s difference between the fans. I looked through the AB documentation to see if the accumulated word should be retained during a power failure and it seems as long as the battery is good (we have no battery light) and power is restored within a half-hour the data would be retained. The rest of the program is retained. I don’t think there is an EEPROM on board. However I’m not sure how to tell if there was or not. How can I determine if an EEPROM is installed?
I will drive the timers with the motor control feedback relay contacts.
Should or is there a way to retain the accumulated word?

Note: There is no (RES) programmed for the counter. Could the un-addressed command be the problem? Where is the (res) command in memory?


Thanks for any help.

Andy

[Kim Gold]

The accumulated value in both the RTO and the CTU will be retained on a power failure. There will probably by an RES in the program somewhere for the CTU instruction. It may even be reset by the 1st scan bit. Maybe there is an instuction to move a zero into the Counter Accumulator. If you have an EEPROM, it may be set to load on powerup, which would overwrite the memory in the PLC. You can check S:5/8 bit, which will be set if the memory module loaded on boot. See the following information which was taken from the taken from the RSLogix 500 help file. It may be of some help.

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Memory Module Loaded on Boot S:5/8

When this bit is set by the processor, it indicates that a memory module program has been transferred to the processor. This bit is not cleared by the processor.

Your program can examine the state of this bit on entry into the REM Run mode to determine if the memory module content has been transferred. Word S:1/15 will be set to indicate REM Run mode entry. This information is useful when you have an application that contains retentive data and a memory module that has only bit S:1/10 set (Load Memory Module on Memory error). Use this bit to indicate that retentive data has been lost. This bit is also helpful when using bits S:1/11 (Load Memory Module Always) or S:1/12 (Load Memory Module Always and Run) to distinguish a power up REM Run mode entry from REM Program (or REM Test) mode to REM Run mode entry.

Password Mismatch S:5/9

This bit is set on REM Run mode entry, whenever loading from the memory module is specified (word 1, bits 11 or 12), the processor user program is password protected, and the memory module program does not match that password.

Use this bit to inform your application program that an auto loading memory module is installed but did not load due to a password mismatch.

Load Memory Module On Memory Error S:1/10

You can use this bit to transfer a memory module program to the processor in the event that a processor memory error is detected at power up. A memory error means the processor cannot run the program in the RAM because the program has been corrupted, as detected by a parity or checksum error. This type of error is caused by battery or capacitor drain, noise, or a power problem.

You must set S:1/10 in the status file of the program in the memory module. When a memory module is installed that has bit S:1/10 set, a processor memory error detected at power up causes the memory module program to be transferred to the processor, and the REM Run mode to be entered.

When S:1/10 is cleared in the memory module, the processor remains in a major fault condition if a memory error is detected on power up, regardless of whether or not a memory module exists.

When S:1/10 is set in the status file of the user program in RAM memory, the memory module must be installed at all times to enter REM Run or REM Test modes.

Load Memory Module Always S:1/11

When this bit is set, you can overwrite a processor program with a memory module program by cycling processor power. A programming device is not required. When this bit is set this overwriting process occurs every time you cycle power.

If you leave the memory module installed, the overwriting process, including data tables, is repeated each time you cycle power. The mode is changed to REM Run each and every power cycle.

The memory module you install in the processor must have status file bit S:1/11 set. Loading takes place if the master password and/or password in the processor and memory module match. Loading can also take place if the processor has neither a password nor a master password.

When S:1/11 is also set in the status file of the user program in RAM, the memory module must be installed at all times to enter the REM Run or REM Test modes.

Load Memory Module and RUN S:1/12

With this bit, you can overwrite a processor program with a memory module program by cycling processor power. A programming device is not required. The processor will attempt to enter the REM Run mode, regardless of what mode was in effect before cycling power.

The memory module you install in the processor must have status file bit S:1/12 set. Loading takes place if the master password and/or password in the processor and memory module match. Loading can also take place if the processor has neither a password nor a master password.

When S:1/12 is set in the status file of the user program in RAM, it does not require the presence of the memory module to enter the REM Run or REM Test mode.