Aliasing tags in Schneider Twido PLC ladder logic

SamyFiny

Member
Join Date
Nov 2020
Location
Joplin Missouri
Posts
4
Hello Every one,
This question came around in my place of work (MOAWP).
It appears very simple on the surface, but I could not get right when I tried.
The question is to provide some sort of aliasing (similar to RSLogix 5000) in the Twido PLC using only the ladder logic available in the programming interface.
In more details, we would have two bits say A and B for example. A program is developed so that these two bits are identical at all times.
So when bit A changes from any states to any states, then Bit B will track it. At the same time when bit B changes then bit, A should track it as well. In addition, all changes must occur in the same CPU scan (this latter condition could be relaxed if it becomes a problem)
I have tried the obvious:
A B
|_______| | _________________________( )
| | |
|
| B A
|_______| | _________________________( )
| | |
|
but this gives a problem when bit A is false, and bit B turns true (externally). You can see that B becomes also false (first rung) as seen from the ladder above, this is because A is false. Then bit B being false will turn off bit A (which was false, to begin with). On the next scan, bit A turns off B.
In the end, we did not achieve the desired result.
Any help will be appreciated
Thanks everyone.
 

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