32 bit addition in SLC

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Aug 2002
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Hi,

Did anyone ever did 32 bit addition in SLC with integer files. I know I can use floating point, but I want to use integer files(NXX:XX). Any help will be apperciated.

Thanks,
 
What do you think this is, a cheap Micrologix?

SLC integer files are strictly 16-bit, so you can't do 32-bit addition in a single register.

Of course, if you can internally call (and on some HMI's even display) 2 consecutive 16-bit registers as one 32-bit register.

If you add the high words of two 16-bit register pairs and the low words of the pairs, you get 32-bit addition, provided that the low word sum is less than 32767.

To get around this, you need to set S:2/14 ("Math Overflow Selected"). When you do the overflow math, the lower registers will still get gibberish in them (probably 32767, but I'm not sure). But in S:13 and S:14, you will have the correct sum (low word/high word).

Move the low word to the desired destination, and add the high word to the high word sum. Be sure to unlatch S:5/0, or the SLC will fault at the end of the scan.

And, of course, if the sum of the high words is greater than 32767, then you're exceeding 32-bit math.

Does that answer the question?
 
NOTE: This is all "as far as I know" info; I don't use 32 bit math often and am not speaking as an expert.

There should be two things you consider before turning on that S:2/14 bit to enable 32-bit math in the SLC.

The first is that now your source arguments are all two words long; you will have to account for that in your data table layout and be extra careful not to accidentally step on the "high word" of your data table.

The second is that the result in the destination address when you enable 32-bit math is not gibberish nor 32767; instead it's the least significant sixteen bits of the resulting 32-bit value. This can be plenty confusing because ordinary comparison instructions will consider it negative if the 16th bit is high.

I did a routine a few weeks ago that put the SLC into 32-bit mode for just one scan, so that my user could perform one 32-bit Subtract and not have to modify the rest of his existing program. I can dig that out if you like.
 
WHAT?

Ken Roach said:
I did a routine a few weeks ago that put the SLC into 32-bit mode for just one scan, so that my user could perform one 32-bit Subtract and not have to modify the rest of his existing program. I can dig that out if you like.

How did you do that? What firmware must I have? Enquiring minds need to know.

Otherwise I too will have to work this out tomorrow. 32 bit motion controllers like 32 bit positions. I did 32 bit math once long ago. What is missing in the above posts is that the carry bit must be used to do the carry when adding ( duh ), and the borrow when subtracting.

Code:
  N7:1 N7:0
+ N7:3 N7:2
  ---------
  N7:5 N7:6

Basically I did it like this:

   CLR N7:9               THIS IS WHERE THE CARRY WILL BE STORED         
   ADD N7:0 N7:2 N7:4     ADD THE LOW WORDS
   XIC S:0/0  MOV 1 N7:9  STORE A ONE IF THERE IS A CARRY
   OTU S5:0               UNLATCH THE OVERFLOW TRAP
   ADD N7:1 N7:3 N7:5     ADD THE HIGH WORDS
   ADD N7:9 N7:5 N7:5     ADD THE CARRY

Allen has pointed out something that I may have overlooked. I should investigate the S:13 and S:14 registers. There may be a simpler way.
Another thing I need to check is clearing the overflow trap. Does this get set when S:2/14 is selected?
I will check that out tomorrow.
 
Peter, I overlooked the Carry bit... you're absolutely right that it's important but I didn't understand the documentation. Thanks very much for weighing in on the discussion.

Regarding running 32-bit math only *some* of the time.....

The SLC-5/03 and higher controllers evaluate the S:2/14 bit only at the end of each program scan. Therefore if you have an existing program that does regular 16-bit math and you don't want to spread out all of your integer storage registers to make room for 32-bit arguments, you're in a bit of a pinch.

My project needed just one 32-bit SUB instruction, and it only needed it every 500 milliseconds or so when the distance value from a DeviceNet linear sensor (Temposonics) needed to be evaluated, in order to determine a very slow velocity of the sensor.

Every 1/2 second, according to the DN bit of a timer, I set the S:2/14 bit = 1 as the very last rung in the main program file.

At the beginning of the main program file, in the very first rung, I jump to a subroutine if S:2/14 is =1. In the subroutine, I perform my 32-bit SUB instruction, and... this is VERY important.... unlatch S:2/14 and include a Temporary End (TND) instruction as the last instruction.

It's the TND instruction that makes the difference. That forces the SLC to stop the program scan, update the I/O, perform housekeeping (including re-evaluating S:2/14 which is now zero) and then take up program execution at the beginning of File 2, where it finds that S:2/14 is no longer true and does not jump to the subroutine.

If the END or RET instructions were used in the subroutine, program execution would continue again *after* the first rung with the JSR, without re-evaluating S:2/14.

This will cause a 1-scan "bump" in the ordinary execution of the SLC program, and I don't know what effect that would have on a high-speed process.
 
Last edited:
Ken:

Did I misunderstand the function of S:2/14? I thought that it only enabled S:13 S:14 to do 32 bit math (as opposed to floating point math).

I didn't realize that the ENTIRE SLC data table would be affected in every math instruction going to an integer. Are you sure about this?

According to the SLC help file, for the ADD instruction:

32-Bit Addition

If you are using a Series C or later 5/02, or a 5/03, 5/04, 5/05 or MicroLogix processor (capable of 32-bit addition and subtraction), you can set the math overflow bit (S:2/14) in the status file. This causes the unsigned, truncated, least significant 16 bits to remain in the destination.

If this bit is not set and an underflow or overflow conditions occurs, the operation will be the same as with a Series B 5/02 processor. The destination address will contain a 32767 (if the result is positive) or -32768 (if the result is negative).

© Rockwell Software 2000

This seems to say that only the low 16 bits are sent to the destination (and not affecting the next word), while the math register would contain both the high and low words.

It will be a while before I'll have access to a SLC to test this for myself. Ron B., do you have time? Peter - I look forward to your report.
 
What do the rookies do when the pros are stumped?

S:2/14 only disables the limiting or saturation at +32767 and -32768.
Ken, I don't think it turns on any 32 bit math functions. If it does, that too will be a new one to me.

The S:13 and S:14 registers are used by the integer multiply and divide routines. They are always used by the multiply and divide routines regardless of how S:2/14 is set. A question I have now is are the results in S:13 and S:14 limited to +32767 and -32768 unless the S:2/14 bit is set. I always set bit S:2/14 so I haver never checked to see how the S:2/14 affects registers S:13 and S:14. I will check that out tomorrow also.

Ken, are you saying that I can't:

Code:
   OTL S:2/14             DISABLE OVERFLOW LIMITING
   CLR N7:9               THIS IS WHERE THE CARRY WILL BE STORED         
   ADD N7:0 N7:2 N7:4     ADD THE LOW WORDS
   XIC S:0/0  MOV 1 N7:9  STORE A ONE IF THERE IS A CARRY
   OTU S5:0               UNLATCH THE OVERFLOW TRAP
   ADD N7:1 N7:3 N7:5     ADD THE HIGH WORDS
   ADD N7:9 N7:5 N7:5     ADD THE CARRY
   OTU S:2/14             ENABLE OVERFLOW LIMITING

Ken, notice that I turned on the S:2/14 just before doing math that may overflow and turned the bit off so that overflows will cause errors in the rest of the program. According to what you say the OTL will not do any good until the end of scan. This seems odd.

More to check out.

Note to all. Most PLCs, microprossers, microcontroller and DSPs are not as heavy handed at preventing the users from ignoring overflows. Most will just set the overflow bit status bit and go on as if nothing happen. Usually the saturation limiting is found only in DSPs and this feature is not on by default. It must be enabled.
 
fRelated topic
I found this the other day which might help those wanting to have the program react differently on every other scan for instance, set S:2/14 on every other scan to do 32 bit math and reset on other scans to do 16 bit math...
Scan Toggle Bit S:33/9
This bit changes state each and every execution of an END, TND, or REF instruction. It is always cleared when entering RUN mode. Use this bit in your user program for applications such as multiplexing subroutine execution.

RSLogix 500 - Copyright Rockwell Software 2000, 2001m
 

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