BSL Example

UL bit goes High at the 33rd bit as expected, but pattern keeps going on. I don't see where you used the UL bit in your example but certainly that is a key.
 
The reference manual seems to assume you don't care about any remaining bits in the array; the examples don't show their state and refer to them as 'invalid'.

Apparently we learn today that the instruction actually shifts whole words only, with the Length parameter controlling how many words and where the .UL is set. A nasty surprise if you actually need it to *only* shift part of a word for whatever reason. You could use a buffer with masked moves to work around it I guess, but imo it should be documented better at the least.
 
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Interesting. At what point does .UL go high? When the bit reaches the 34th position? Or when it shifts out the end of the second DINT?

EDIT: Based on instruction reference manual, .UL is set by the bit unloading from the point specified by your length, and remaining bits in the array are 'invalid'.




I see the same thing: the 1 bit is in L10:2/1 i.e. the 66th bit of the array when control R6:0.UL is 1 i.e. on the scan when R6:0.UL was shifted out of L10:2/0 [R6:0.LEN]th (= 65th) bit.



See below; the 1 bit was still present further on in the first (low) word of L10:2 when I pressed [Print/SysRq] to get the screen shot, but the location of the 1 bit in L10:4/1 means it was in L10:2/1 when copied on Rung 0002 when R6:0.UL had a rising edge.

yyy.png
 
Well shoot, that's not gonna work for me then.
Hol' on there, Baba Louie!


Yes, using [XIO R6:0.UL] to short-circuit the rising edge of the rung feeding the BSL results in the 36th bit (L10:1/3) becoming 1 when R6:0.LEN is 35:


yyy.png

But you could simply set the length one short of where you want it to stop, but then you could not stop on the first bit of any DINT, at least not without jumping through some hoops.


However, using instead [XIO L10:1/2] as the short circuit makes the bit stop at that 35th bit (L10:1/2):


zzz.png


For that matter, the [XIO L10:N/M] is the key, and the R6:0.LENGTH is irrelevant as long as the length covers the last possible position at which you might want the 1 bit to stop.
 
This works, Just clear the second array. Seems obvious now. ...




Ah, if it is supposed to auto-repeat (I forgot the "starting over" from the OP), then yes, even better.


Cannot help but ask, why not have the rising edge drive a counter and use the counter.DN to reset and resart the counter, much the same way the timer reset is used in these examples?
 
This works, Just clear the second array. Seems obvious now.

That should work fine if you just need the remainder of the array to be blank and you can guarantee you'll only have a single high bit at a time being shifted in it.

Should you need to preserve the state of the array beyond the end of your shifted Length, a pair of MVM should do the trick -- one before the bit shift copying to a buffer location, one after copying it back.
 
Using a counter would just be extra, I don't see the need, the Length appears to do the job for now. You disagree?


I do not disagree if you are using the values of the bit along the way for summat else.


That said, I don't see any significant advantage of [XIC L10:0/5] vs. [EQU counter.ACCUM 6].


Sidebar: an unconditional [OTU dint_array[M].N] will do the same thing as the control.UL in your example, and also requires only one thing to fix if the final position before the reset may change over time, as long as counter.LENGTH is oversized.
 
I just had to jump back in here to try and clarify a few things that I see seem to be misunderstood.

I took some time to verify the timing of the S:4 word
In your example you use bit S:4/13 to trigger the BSL we should stop and understand just what bit S:4/13 is and how it works. The hole word S:4 is a binary free running clock that runs whenever power to the plc in on. Bit 0 (S:4/0 ) changes state every .1 ms ( .1 Millisecond) that means that bit 0 will be true for .1ms and false for .1ms and repeat the word value will change every .1 ms
Bit 13 will change state every 819.2 ms ( that’s false to true or then true to false)
You will only get a false to true transition every 1.196 sec (2 X 818.2 ms)
Bit 15 of S:4 will change state every 3.768 sec or transition from false to true every 6.536 sec
This all happens as long as power is we have no control of this clock all we can do is read the value or the bits as we need them.

In your example the rung would evaluate true once every 1.196 sec
if the rung evaluates to true and BSL would execute every 1.192 sec and the bits would shift each time and the value of both DINT words would change depending on the value of the their bits.

While I would expect the full scan time of the ladder would be typically be about 150 ms or so depending on the size and complexity of the program.
The BSL would never execute every scam of the ladder code. As I explained earlier, the BSL function will only execute when the rung preceding the BSL is scanned and transitions from false to true
When that transition happens the BSL .EN bit is set and if the BSL.DN bit is false, the BSL is executed as described earlier, on the completion of shifting the bit values and the input value is copied to bit 0 (true or false) of the array (DINT) the BSL.DN bit is set to true it will remain true and the BSL will not execute again until the BSL.EN bit is cleared (False) then the BSL.DN bit is also cleared
It may help to think of the .EN and .DN bits as housekeeping bits in the BSL
The BSL is not dependent on the State of the EN bit but rather the .EN bit is dependent on the state of the rung preceding BSL. It is set when the rung evaluates to true so setting or clearing the .EN bit has no real value except it will increment the shift for each scan of the ladder if the rung is true
When the rung is true and the BSL executes the rung scan is suspended while the BSL executes and continues after the .DN bit is set
All this happens so fast you will never see it all you will see is the value of the DINT words may have changed if the bit pattern has changed.
We should not interchange the ladder program scan and a function like BSL execution they are much different

I hope this helps to understand how a BSL works
 
In your example the rung would evaluate true once every 1.196 sec

I think you have a typo there; it's actually 1.6384s (twice 2^13 = 8192 cycles of the 10Khz free-running clock(FRC) => 8192clock-cycle/bit-transition * 2bit-transition/bit-13-cycle * 1e-4s/clock-cycle).


While I would expect the full scan time of the ladder would be typically be about 150 ms or so depending on the size and complexity of the program.


Yes, agreed: if the per-scan time of the ladder program (S:35, IIRC) is longer than the bit-cycle of the chosen FRC bit then the program would likely miss some rising edges.


The BSL would never execute every scam of the ladder code. ...





Actually this is only true in typical operation i.e. if the code does not poke the control structure's bits apart from what happens in the BSL instruction.


If you duplicate my code in post #7, then you will see that the BSL behavior can indeed be tricked into shifting the bits every scan.


The key is to recognize that the only way to detect a "rising edge" of a bit is to know (i.e. store) the state of that bit from the previous scan (N.B. GaryS, in his last post, basically says just that in between the lines).


So the concept of "rising edge" actually involves the combined states of two bits: the source bit which has the rising edge to be detected; the storage bit which contains the state of the source bit from the previous scan.


I.e. in ladder, the rising edge detection looks like this:


Code:
 source_bit                      storage_bit
-----] [-----+------------------------( )------------+---
             |                                       |
             |  storage_bit     rising_edge_bit      |
             +-----]/[----------------( )------------+
The point is that state of the [rising_edge_bit] is dependent on the states of both the [source_bit] and the [storage_bit].


So if, after that previous rung, another rung were added like this:



Code:
     force_rising_edge            storage_bit
 -----------] [------------------------(U)------
Then, whenever [force_rising_edge] was 1, the [rising_edge_bit] will be assigned a 1 on every subsequent scan that [source_bit] was 1.


What I was doing in the example in post #7 was just that i.e. putting a 0 into the [storage bit] (i.e. R6:0.EN) of the BSL's [rising edge-detection] machinery.


Play it in your head, or better yet, code my example in post #7 and run it: you will see the 1 bit jump 8 positions, from L10:0/7 to L10:0/15 (actually it takes 8 scans; with no other code running that takes less than 10ms, so it appears to be instantaneous).
 
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Interesting yes i entered the wrong number it should be 1.6384 sec or 2 X .8192
and yes you could force the BSL to execute every scan maybe but to do that you will need to clear both the .EN and .DN bits every scan
i an not even sure that will work because the function may not recognize the .DN bit or the .EN bit change of state until it tries to run the BSL at that time it may just update the bits and return to them actually run it on the next ladder scan
it would be interesting to test it and see all the functions are subprograms that are called from the main how is the data handled within them can it be changed external to subprogram or dose it need to be called to update the data
where are you getting a clock pulse of 10Khz for the free running clock the CPU clock pulse would be closer to 100Mhz and I have confirmed that the S:4/0 changes state every .1 ms that is .00001 sec and with that the value of the word will count up by .1 ms the resolution of the word is .1 ms
bit 13 will only change state every 819.2 ms nd it will take 2 changes true to false and false to true on the next 819.2 ms so the time is correct 1.6384 sec
i did check and verified this information before my last post
but why would want to update the BSL on every scan you can't even bring in the I/O that fast you would be using a lot of processor time to do nothing
 

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