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Old May 28th, 2015, 01:36 PM   #1
bernie_carlton
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PLC rung scan implications

I have often seen statements that arranging rungs so that the condition most likely to make the whole rung TRUE (or FALSE) should be placed to be evaluated first to speed up scan time.

This implies that, upon determining that the rest of the rung conditions are irrelevant to deciding the ultimate TRUE or FALSE state of the rung, the system will bypass (or in some way shorten the evaluation of) further conditions and jump right to output processing.

While this sounds efficient does anyone have a reference to an official technical publication which specifically states this behavior in the evaluation of rungs? (I'm thinking primarily Allen Bradley or AutomationDirect PLCs since those are the ones I'm most familiar with.) I'm looking not just for a recommendation of rung structure but an actual statement as to how this 'evaluation shortening' takes place.
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Last edited by bernie_carlton; May 28th, 2015 at 01:37 PM. Reason: Title misspelling
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Old May 28th, 2015, 02:18 PM   #2
RonJohn
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Not sure if a technote qualifies as "official technical publication" but Rockwell Technote ID 47165 does state "For optimal performance of a series of instructions, sequence the instructions from the mostly to be false on the left to the least likely to false on the right." and goes on to briefly explain why.
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Old May 28th, 2015, 02:27 PM   #3
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I was told this in an Allen Bradley class many years ago ( PLC5 class). I believe it was in a training manual. ( don't have the manual anymore though)

But see link and attached pdf. (tip at bottom of page)

https://www.google.com/url?sa=t&rct=...zay5ZpQUXpExUA
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Old May 28th, 2015, 02:39 PM   #4
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Given the 'tip' I see how the scan of series contacts can be optimized.

I don't see that the advice carries over to a parallel circuit. The 'rung condition in' would be the same for all contacts in a parallel branch even if the top most branch evaluates as TRUE.
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Old May 28th, 2015, 02:45 PM   #5
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I'm doing some inferring here but I would have to think there is a processor optimization that will skip the load/evaluate sequence of an instruction if the rung-condition-in to a series instruction is false, since the state of that instruction wouldn't matter anyway. That is a far cry from skipping to the end of the rung immediately but it could (possibly) cut the total clock cycles to evaluate a series string pretty significantly, especially if it doesn't need to fetch/load data.

This would also seem to indicate that you could get a pretty significant boost if you put the series instructions first in a series-parallel rung.

Keith
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Old May 28th, 2015, 02:52 PM   #6
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Quote:
Originally posted by bernie_carlton:

I don't see that the advice carries over to a parallel circuit.
The info doesn't specifically speak to this. It seems to me the only way you could make this work optimally is to add a bunch of code "under the hood" that checks the status of a branch and exits the structure early if a branch evaluates true. But from a processing standpoint the break-even point would be half way down the branch set. If you make it past half way you could end up costing yourself time, which seems like a pretty precarious optimization.

Keith
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Old May 28th, 2015, 05:28 PM   #7
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Quote:
Originally Posted by bernie_carlton View Post
I don't see that the advice carries over to a parallel circuit. The 'rung condition in' would be the same for all contacts in a parallel branch even if the top most branch evaluates as TRUE.
The parallel situation is handled similarly to the series - the first TRUE branch in a series of branches stops further processing of succeeding branches and moves to the branch end. Refer to page C-5 in the manual linked below

http://www.futuronix.in/automation-m...B_MANUAL_I.pdf
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Old May 28th, 2015, 07:05 PM   #8
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Thank you Doug. That's about as clear of a statement as there is. It would be neat to be able to see the internal workings of that algorithm but this probably has to be it. Assuming this applies to other AB systems ladder interpretation methods then I'm satisfied about that.
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Old May 28th, 2015, 07:23 PM   #9
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Quote:
Originally Posted by Doug-P View Post
The parallel situation is handled similarly to the series - the first TRUE branch in a series of branches stops further processing of succeeding branches and moves to the branch end.
This may be the case for SLC/Micro/PLC5, but not for the CLX series...I can't give you any documentation to back it up, but you can do something like this, and the ADD instruction will execute, so clearly it keeps processing the nested branches
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Old May 28th, 2015, 07:28 PM   #10
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The technote from post #2 backs this up, in that "The controller executes all instructions on a rung". I learned this the hard way when I AFI'd out a rung that kept faulting the processor randomly, until I had more time to track down the issue, and it still kept faulting the processor. Just because the rung in condition to every other instruction on the run could never be anything but false, that didn't stop it from evaluating each instruction and checking them for validity.

The technote also notes that if an instruction's rung in condition is false, an instruction will execute faster than if it is true, so the comments about putting instructions most likely to be false at the start of a rung speeding up the scan time, do hold true.
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Old May 28th, 2015, 08:07 PM   #11
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Quote:
Originally Posted by ASF View Post
This may be the case for SLC/Micro/PLC5, but not for the CLX series...I can't give you any documentation to back it up, but you can do something like this, and the ADD instruction will execute, so clearly it keeps processing the nested branches
Yes, there are lots of differences between SLC and CLX. I wonder, regarding the example you posted, might the processor 'know' that the ADD instruction is somehow different and should still be processed? Is it still executed if there's a FALSE condition preceding it on the same branch leg?
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Old May 28th, 2015, 08:13 PM   #12
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Quote:
Originally Posted by Doug-P View Post
Is it still executed if there's a FALSE condition preceding it on the same branch leg?
Pretty safe to say that would be a negative no matter which processor your using.
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Old May 28th, 2015, 08:16 PM   #13
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Quote:
Originally Posted by Bering C Sparky View Post
Pretty safe to say that would be a negative no matter which processor your using.
I guess all I can say to that is
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Old May 28th, 2015, 08:38 PM   #14
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Quote:
Originally Posted by Bering C Sparky
Pretty safe to say that would be a negative no matter which processor your using.
Well, actually, the instruction would still be executed. It's just that the instruction does different things depending on whether its rung in condition is true or false when you execute it.

If the rung in condition is true, it will add source A to source B, store the result in dest, and then set its rung out condition to true

If the rung in condition is false, it will do nothing with the source or destination values, and then set its rung out condition to false

Quote:
Originally Posted by Doug-P
I wonder, regarding the example you posted, might the processor 'know' that the ADD instruction is somehow different and should still be processed?
As the technote said, in a CLX, all instructions on a rung are executed. It's just that each instruction does different things based on the state of it's rung in conditions.
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Old May 28th, 2015, 09:07 PM   #15
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ASF,
That makes perfect sense, if the output (which the add would be) is true go and write a 1, if the output is false go and write a 0.
So it will be read and execute something each scan even if it all takes place under the hood.

I was only referring to the add will not increment if there is a false preceding it in my last post.

BCS

Edit, I Realize that the value in questions is not a bit but if we are using N7 then then most likely a INT so it will be at the word level not bit, but the example I used is the same principal.
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