Maximizing PLC Scan Rate

[CapinWinky]

Rockwell uses 32bits of memory to store INT and SINT, all integers on a Compact/ControlLogix are treated internally as 32bit. They say they are doing this for performance reasons. Other VxWorks implementations use 16 and 8 bits of memory for INT and SINT respectively and there is no performance ding.
SINT1:= SINT2 + SINT3;
executes exactly as fast as
DINT1:= DINT2 + DINT3;
on normal 32bit systems without reserving 32bits for each SINT.

There is plenty of memory, so it's not a big deal, it's just weird. I'm speculating that the particular CPU they selected had some quirk about it and they did this to get around it.

 

[daba]

Rockwell's implementation of data storage is a minimum of 32-bits for a single tag, which makes sense since the data memory is embedded inside the tag's "structure" in the database.

This is not the case for INT and SINT Arrays, however. The INTs and SINTs are "packed" into the 32-bit memory spaces, 2 INTs or 4 SINTs.

Converting single-tag SINTs/INTs to DINTs, and vice-versa, entails relocation of the sign bit, and zeroing "unused" bits. I fail to see how that can be accomplished in one clock cycle.

Converting Array tags, however, involves much more, eg. moving groups of 8 or 16 bits out, and read/modify/write to put them back as destination. These operations will certainly require more than one clock cycle.

 

[rdrast]

Along with what Daba says, the Logix microprocessor is a full 32 bit processor. It does not address memory byte by byte, but full 32 bit word by word.
With any microprocessor, dealing with its native word size is always the most efficient way to go.