Hello everyone,
I am new to the forum and I am currently working on a program that converts FBD schematics to Ladder Logic targeting Allen Bradley RSLogix500
The export format I am using is the SLC library file format, which is the only ASCII based format supported by RSLogix.
I’ve came across a serious bug while importing the SLC files I generate. The bug can be replicated easily by
A. Creating any ladder logic program, assigning initial values to the I/O.
B. Saving the file as an SLC library file.
C. Closing the file and the reopening it.
D. You will now notice that not all the initial values show up in the data files.
I am attaching an slc file that demonstrates the problem
(the forum doesn't allow an slc attachment so please rename the file from init.txt to inti.slc)
Cpu :
START 1747-L551B % 1747-L551B/C 5/05 CPU - 16K Mem. OS501 Series C FRN 3-9 %
IO Slots :
SLOT 1 1746-I*8 % Any 8pt Discrete Input Module % SCAN_IN 1 SCAN_OUT 0 IOCARD -6448 24 14890 176 6496 212 -28694 116 76 237 24 0
SLOT 2 1746-I*8 % Any 8pt Discrete Input Module % SCAN_IN 1 SCAN_OUT 0 IOCARD -6448 24 14890 176 6496 212 -28694 116 76 237 24 0
SLOT 3 1746-O*8 % Any 8pt Discrete Output Module % SCAN_IN 0 SCAN_OUT 1 IOCARD -6448 24 14890 176 6496 212 -28694 116 76 237 24 0
Data Files :
DATA O:3
% O:3.0 % 0X0008
DATA I:1
% I:1.0 % 0X0002
DATA I:2
% I:2.0 % 0X0004
The bug is that even if I:2.0 has the value 4 it is not imported by RSLogix which shows 0 when imported
So RSLogix cannot basically import its own export correctly.
I would appreciate any help on this
I am new to the forum and I am currently working on a program that converts FBD schematics to Ladder Logic targeting Allen Bradley RSLogix500
The export format I am using is the SLC library file format, which is the only ASCII based format supported by RSLogix.
I’ve came across a serious bug while importing the SLC files I generate. The bug can be replicated easily by
A. Creating any ladder logic program, assigning initial values to the I/O.
B. Saving the file as an SLC library file.
C. Closing the file and the reopening it.
D. You will now notice that not all the initial values show up in the data files.
I am attaching an slc file that demonstrates the problem
(the forum doesn't allow an slc attachment so please rename the file from init.txt to inti.slc)
Cpu :
START 1747-L551B % 1747-L551B/C 5/05 CPU - 16K Mem. OS501 Series C FRN 3-9 %
IO Slots :
SLOT 1 1746-I*8 % Any 8pt Discrete Input Module % SCAN_IN 1 SCAN_OUT 0 IOCARD -6448 24 14890 176 6496 212 -28694 116 76 237 24 0
SLOT 2 1746-I*8 % Any 8pt Discrete Input Module % SCAN_IN 1 SCAN_OUT 0 IOCARD -6448 24 14890 176 6496 212 -28694 116 76 237 24 0
SLOT 3 1746-O*8 % Any 8pt Discrete Output Module % SCAN_IN 0 SCAN_OUT 1 IOCARD -6448 24 14890 176 6496 212 -28694 116 76 237 24 0
Data Files :
DATA O:3
% O:3.0 % 0X0008
DATA I:1
% I:1.0 % 0X0002
DATA I:2
% I:2.0 % 0X0004
The bug is that even if I:2.0 has the value 4 it is not imported by RSLogix which shows 0 when imported
So RSLogix cannot basically import its own export correctly.
I would appreciate any help on this