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Old July 27th, 2021, 08:14 PM   #1
TheWaterboy
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Splitting a word into integers

I have to take a 16 bit N register and split some of the bits into separate integers. example:

Bits 0-1 = integer with a value from 0-3
Bit 2 is a bool = easy one
Bits 3-12 = another integer value from 0-1023
remainder are bools
How do I split a word in this way? Is Mask and shift the only way?
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Old July 27th, 2021, 08:20 PM   #2
Phrog30
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For AB/Rockwell I'd use BTD.
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Old July 27th, 2021, 08:28 PM   #3
drbitboy
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Quote:
Originally Posted by TheWaterboy View Post
I have to take a 16 bit N register and split some of the bits into separate integers. example:

Bits 0-1 = integer with a value from 0-3
Bit 2 is a bool = easy one
Bits 3-12 = another integer value from 0-1023
remainder are bools
How do I split a word in this way? Is Mask and shift the only way?

I think I have seen a PLC instruction that does this in one go, but I forget which manufacturer that was. [Update: @Phrog30 knew it]

Mask and divide* is an equivalent alternative if there is no multi-bit-shift instruction, but yes, those are the most direct ways I can think of.

* or divide then mask, to get around a non-zero sign bit
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Old July 27th, 2021, 10:12 PM   #4
GaryS
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A masked move for each set would give you what you are looking for
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Old July 27th, 2021, 10:28 PM   #5
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For positive integers with a zero most-significant bit Divide and then AND mask should work - assuming the PLC does a normal truncating integer division. It may not work in a PLC that insists on doing roundoff with integer division. Some processors divide integer 5 by integer 3 to get a result of integer 2.

I'm not sure how well divide and mask can work when starting with a negative number.

Shift and Mask solutions are best done in that order - shifting first and then masking. C programmers tend to do that because you do not have to worry as much about what the processor is doing with the shift - if it is pushing in a carry bit, doing sign extension, etc.

The non-elegant PLC solution is to initially zero all the bits of the result register and then load it bit by bit from the parts of the original register using contact and coil logic. It sounds crude but at least you're not at the mercy of how the PLC chooses to do it's math. It's more rungs but they're not hard to understand.
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Old July 27th, 2021, 10:38 PM   #6
dmroeder
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Would a MVM work? TheWaterboy wants bits 3-12 to represent and integer (0-1023). Those bits need to be "moved" to bit 0 of an integer. As Phrog30 says, this is what BTD does. Map "these bits" to "those bits".
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Old July 27th, 2021, 10:58 PM   #7
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Quote:
Originally Posted by Corsair View Post
For positive integers with a zero most-significant bit Divide and then AND mask should work - assuming the PLC does a normal truncating integer division. It may not work in a PLC that insists on doing roundoff with integer division. Some processors divide integer 5 by integer 3 to get a result of integer 2. ...

d'Oh! I knew that, but forgot!
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Old July 27th, 2021, 11:19 PM   #8
GaryS
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The masked move MVM for bits 3 - 12 would be 0 or 8 - 1023
You could do bit shift right on the results may be better
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Old July 27th, 2021, 11:37 PM   #9
drbitboy
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Single-instruction alternative to MVM+[shift or divide]:
  • CPT tenbits_12_to_3 (sixteenbits AND 8184)/8
mask of 8184 = (2**13)-8
Code:
$ python
Python 3.8.8 [...]
>>> bin(8184)
'0b1111111111000'
   2109876543210
   111
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Old July 28th, 2021, 02:56 AM   #10
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I always have to preface my comments with "I know nothing about rslogix", almost.
Is it accurate that the OP is RSLogix 500 and BTD is RSLogix 5000?
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Old July 28th, 2021, 05:25 AM   #11
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Quote:
Originally Posted by kalabdel View Post
Is it accurate that the OP is RSLogix 500
we don't know?
Quote:
Originally Posted by kalabdel View Post
and BTD is RSLogix 5000?
yes, also RSLogix 5/PLC-5.

P.S. MVM+shift is less useful than AND+shift here as MVM does not clear higher bits. Does BTD clear destination INT's bits outside its mask?

P.P.S. this could also be done with two shifts, left then right, assuming the right-shift does not fill with 1s from the left when the sign bit is 1; divide will always fill with 1s from the left, for negative signed integers, so, if unsigned integers are used, then extra steps must be taken when the high bit in the range is the sign bit.
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Last edited by drbitboy; July 28th, 2021 at 05:52 AM.
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Old July 28th, 2021, 06:05 AM   #12
drbitboy
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Oh, and CCW? Yeah, it has a multi-bit right shift, but the manual has not a whit of a whisper of a ghost of a clue what it does about the sign bit

yyy.png


ROTFLOL
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Old July 28th, 2021, 09:51 AM   #13
dmroeder
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Quote:
Originally Posted by kalabdel View Post
Is it accurate that the OP is RSLogix 500 and BTD is RSLogix 5000?
I really need to work on my reading comprehension This is an important distinction, I should have paid closer attention to that detail. OP doesn't mentions SLC specifically, but does mention "N" data files.
  • BTD in RSLogix5 = Yes
  • BTD in RSLogix500 = No
  • BTD in RSLogix5000 = Yes
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Old July 28th, 2021, 11:27 AM   #14
TheWaterboy
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Sorry for missing the model number. I work in a silo and forget there are other models

The source is a ML1400 so Logix 500. The eventual designation of all this will be a CLX so BTD is available on that end, but I would prefer to convert it at the source.

I will be back at this in about 4 hours (if things go well this morning) and try again.
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Old July 28th, 2021, 02:33 PM   #15
drbitboy
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Here is why you want to use BTD or even looped shifts, and not DIVides.
Attached Files
File Type: pdf andshftint.pdf (319.2 KB, 12 views)
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