homework help

dragonball

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I am tryin to create the subroutine that triggers by each second.DN but it's not moving my SQO.
Is there anything wrong with my instruction?

testing.JPG
 
second.DN is 1 on the left when the JSR executes i.e. calls the subroutine, so the [XIO second.DN] will be False whenever the subroutine on the right is executing. That is why the SQO on control_1 never fires.


But even if you change that to [XIC second.DN], it will never fire, I think, because the SQO executes on the "rising edge" of its input rung, and that rung ([XIC second.DN])will always be True when the subroutine is called.


So the problem is that, normally, for the SQO instruction to fire, it needs to (think it) see a "rising edge," which means it needs to see its input rung False on one scan and True on the next. Normally (hint hint). But since that subroutine is only called when second.DN is 1, that rung will never be False; in fact, you can remove the [XIO/XIC seconds.DN] on that rung.


There is a way around this, and it is an abnormal way to use the SQO instruction.


You are very close; it will only take one more instruction, and the [XIO second.DN] on the input rung can be removed. I don't want to give you the answer right away so you can have the satisfaction of finding it yourself, which is the same way someone did it for me.


The key is the answer to this question: "What input conditions (plural!) make the SQO fire i.e. how does the SQO detect, or define, a rising edge of its input rung, between one scan and the next?" To see it you need to look at the flow chart on page 604, four pages after here - what conditions make it follow those first two right-hand :"YES" choices? If you can instantiate those conditions every time the subroutine is called, then that SQO will think it has a "rising edge," and it will fire every time the subroutine is called.
 
Last edited:
dragonball said:
so, what should I do to make second.DN true in subroutine?
make it opposite?
Click to expand...


Actually, remove any test of second.DN in the subroutineL the only time that subroutine is called is when second.DN is 1, so there is no need to test second.DN in the subroutine.
 
I found like if DN is true then EN is set to be true, but it did not work out.

I tried all the trigger related to timer, but I couldn't figure out.

is there any more hint?
 
drbitboy said:
The key is the answer to this question: "What input conditions (plural!) make the SQO fire i.e. how does the SQO detect, or define, a rising edge of its input rung, between one scan and the next?" To see it you need to look at the flow chart on page 604, four pages after here - what conditions make it follow those first two right-hand :"YES" choices? If you can instantiate those conditions every time the subroutine is called, then that SQO will think it has a "rising edge," and it will fire every time the subroutine is called.
Click to expand...

sorry I got even more confused with the tree explanation.
if second.DN is true, and EN is also true, then I need to put second.EN in subroutine?
I tried that but it did not work.
 
Your second.DN flag is the equivalent of Shroedinger's cat in your mind, but it's not in the PLC logic and how it works.

You should review how the PLC executes the logic, how global scoped variables work and why you shouldn't read output variables, particularly in a Logix 5000 platform.

Have you ever been taught the method of tracing a program by hand? In an Excel sheet the first column is the cycle and number it from 0 to 10 or 100. The remaining columns are the variable names in the piece of logic you're debugging.
Write down the values of the variables in the first line, then you do the logic in your head and write down the values of the variables in line 1 and so forth until you understand why things aren't triggering.
 
There are two principles that you need to understand to grok PLCs (or any computer that is programmed). The first is this: the only thing worse than a PLC not doing what you want it to do, is when it does exactly what you told it to do, and it always does the latterl; stated another way, the PLC cares not a whit what you want it to do, but it very carefully and precisely does what you tell it to do. The second principle is covered below.

dragonball said:
I found like if DN is true then EN is set to be true, but it did not work out.
Click to expand...

Haha, it's that moment of dawning comprehension that we live for.

Look at what you wrote there: "if DN is true, then EN is [assigned]* to be [1]*." You are very close: you are talking about OUTPUT action by the SQO, but the original question was about the INPUT states that trigger (fire) the SQO.

Think about that for a second, and ask yourself two questions

  • In that case, i.e. where "EN is assigned to be 1," what was EN before it was assigned to be 1?
  • Would the logic of the flow chart reach that box, which assigns 1 to EN, if EN was not that previous value?
Don't read any further until you know in your bones the answers to those two questions. I know you want to move on, and probably feel like we are playing games when we could just give you the answer, but I assure you we are not: when you get it, programming PLCs will never be the same; we are trying to get you to think less smart and more stupid i.e. to think like a PLC; this is the essence of my .sig(nature) below.

If you are not smart enough to figure it out, then frankly we would all prefer you not take up a career in this industry, because someone could get hurt, and that someone could be us. BUT, we can see from your existing code that you are smart enough to get this on your own, and that you are only having a bit of temporary coder's block; but I digress so let's not bother with branches that will never be followed (see what I did there ;)?).

Below is the logic for a one-shot (rising-edge; ONS; OSR; etc.).

Code: 
  input_bit        ibals    rising_edge_detected
1----] [-----2+----3]/[---------------4( )-------5+--9--
              |6                                  |8
              |                       ibals       |
              +-----------------------7( )--------+
 
* ibals:  input_bit after last scan
This is one of those times when the second principle (mentioned above) of "left to right, top to bottom" is important: the PLC executes a program; that program is a sequence of steps; the sequence in which the steps are executed is (sometimes) critical to correct operation of the program i.e. critical to ensuring the PLC does exactly what we want it to do. Note the sequence of the rung above:

  1. Start the rung in a true state on the LEFT (left to right), [XIC input_bit] => "look for a 1" in the XIC's Boolean [input_bit]:
    1. If [input_bit] has a value of 0, then the rung state after (to the right of) the XIC will be false;
    2. if [input_bit] has a value of 1 AND the rung state before the XIC was true, then the rung state after the XIC will be true.
      1. Since the rung to the left of the XIO connects to the left-hand rail, its state will always be true in this case.
  2. Hit a branch, follow the TOP path (i.e. too to bottom)
  3. [XIO ibals] (left to right) => "look for a 0:"
    1. if the XIO's Boolean [ibals] has a value of 1, then the rung state after the XIO will be false;
    2. if [ibals] has a value of 0 AND the [rung state before the XIO] is true, the rung state after the XIC will be true.
      1. This is the key point; looking back to the XIC, and restated it says if "[input_bit] on this scan is 1 AND [input_bit] was 0 on the last scan," then the XIO's output rung will be true.
  4. [OTE rising_edge_detected] (left to right) => assign either 0 or 1 to OTE(4)'s output bit [rising_edge_detected]:
    1. If the state of the rung to the left of the OTE(4) is false, then assign a 0 to [rising_edge_detected]
    2. If the state of the rung to the left of the OTE(4) is true, then assign a 1 to [rising_edge_detected]
      1. Here is the payoff for the key point above (3.2.1): that rung state is true if, and only if, [input_bit] on this scan is 1 AND [input_bit] was 0 on the last scan.
  5. End of the top branch, so the next step is to ...
  6. ... start bottom branch (top to bottom)
  7. 7 [OTE ibals] (left to right) => assign either 0 or 1 to OTE(7)'s output bit [ibals]:
    1. The way this is arranged, after this OTE(7), [ibals] will have the same value as input_bit had at the beginning of this scan, which means that, at the start of the next scan, [ibals] will have the value of "[input_bit] after last scan."
  8. End of the bottom branch, no more top to bottom available, so ...
    1. There is an OR calculated from the states the two rungs that join here, but it is irrelevant for this particular case.
  9. finish the rung (left to right).
To be sure, that was painful to read, even more painful to write; however it is the only way to truly understand, and learn, what it is to think like a PLC; over time you will inculcate that process to the point is will be as simple and painless as reading this sentence.

But the payoff is, now you should know exactly how rising edge detection works, be it written explicitly with XIC/XIO/OTE, or encapsulated in any of a number of instructions with various names (ONS; OSF; OSR; -]P[-; -]N[-; -]^[-; -]v[-; P_TRIG; N_TRIG; CTU; CTD; SQO; etc.).

So the sixty-four thousand dollar question to you, on which your entire career in PLCs depends, is this: which bit in the SQO control struct is the equivalent to [ibals] in the example above? What does the state of that bit need to be to trigger the SQO. Obviously second.DN is the analog for [input_bit], or even a naked (i.e. connected to the left rail), and therefore true, rung would work. But what bit holds that key bit of information "Hey Mr. PLC, on the previous scan, the input rung state was X?"

* the phrases "set/reset" and "true/false" have special meanings, so there is less ambiguity when using "assign" and "0/1" the value of Boolean tags (bits).
 

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